# Confidential Machine Learning within Graphcore IPUs

arXiv: https://arxiv.org/abs/2205.09005 · HTML: https://mlsanity.com/paper/2205.09005/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 8 of its 43 references that are in the map.
- First posted on arXiv 18 May 2022.

## Builds on (most cited first, 8 of 8)

- [In-Datacenter Performance Analysis of a Tensor Processing Unit](https://mlsanity.com/paper/1704.04760/) (2017)
- [Slalom: Fast, Verifiable and Private Execution of Neural Networks in Trusted Hardware](https://mlsanity.com/paper/1806.03287/) (2018)
- [CryptGPU: Fast Privacy-Preserving Machine Learning on the GPU](https://mlsanity.com/paper/2104.10949/) (2021)
- [Chiron: Privacy-preserving Machine Learning as a Service](https://mlsanity.com/paper/1803.05961/) (2018)
- [ShEF: Shielded Enclaves for Cloud FPGAs](https://mlsanity.com/paper/2103.03500/) (2021)
- [SGXIO: Generic Trusted I/O Path for Intel SGX](https://mlsanity.com/paper/1701.01061/) (2017)
- [Customizing Trusted AI Accelerators for Efficient Privacy-Preserving Machine Learning](https://mlsanity.com/paper/2011.06376/) (2020)
- [Towards a Trusted Execution Environment via Reconfigurable FPGA](https://mlsanity.com/paper/2107.03781/) (2021)

## Built on by (most cited first, 2 of 2)

- [Reducing Memory Requirements for the IPU using Butterfly Factorizations](https://mlsanity.com/paper/2309.08946/) (2023)
- [Privacy-Preserving and Trustworthy Deep Learning for Medical Imaging](https://mlsanity.com/paper/2407.00538/) (2024)

## Abstract (arXiv)

We present IPU Trusted Extensions (ITX), a set of experimental hardware extensions that enable trusted execution environments in Graphcore's AI accelerators. ITX enables the execution of AI workloads with strong confidentiality and integrity guarantees at low performance overheads. ITX isolates workloads from untrusted hosts, and ensures their data and models remain encrypted at all times except within the IPU. ITX includes a hardware root-of-trust that provides attestation capabilities and orchestrates trusted execution, and on-chip programmable cryptographic engines for authenticated encryption of code and data at PCIe bandwidth. We also present software for ITX in the form of compiler and runtime extensions that support multi-party training without requiring a CPU-based TEE. Experimental support for ITX is included in Graphcore's GC200 IPU taped out at TSMC's 7nm technology node. Its evaluation on a development board using standard DNN training workloads suggests that ITX adds less than 5% performance overhead, and delivers up to 17x better performance compared to CPU-based confidential computing systems relying on AMD SEV-SNP.