# Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

arXiv: https://arxiv.org/abs/2205.08524 · HTML: https://mlsanity.com/paper/2205.08524/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- Builds on 0 of its 12 references that are in the map.
- First posted on arXiv 17 May 2022.

## Built on by (most cited first, 4 of 4)

- [Hybrid Intelligent Testing in Simulation-Based Verification](https://mlsanity.com/paper/2205.09552/) (2022)
- [Review of Machine Learning for Micro-Electronic Design Verification](https://mlsanity.com/paper/2503.11687/) (2025)
- [Active Learning For Repairable Hardware Systems With Partial Coverage](https://mlsanity.com/paper/2503.16315/) (2025)
- [Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closure](https://mlsanity.com/paper/2610.17449/) (2026)

## Abstract (arXiv)

Constrained random test generation is one of the most widely adopted methods for generating stimuli for simulation-based verification. Randomness leads to test diversity, but tests tend to repeatedly exercise the same design logic. Constraints are written (typically manually) to bias random tests towards interesting, hard-to-reach, and yet-untested logic. However, as verification progresses, most constrained random tests yield little to no effect on functional coverage. If stimuli generation consumes significantly less resources than simulation, then a better approach involves randomly generating a large number of tests, selecting the most effective subset, and only simulating that subset. In this paper, we introduce a novel method for automatic constraint extraction and test selection. This method, which we call coverage-directed test selection, is based on supervised learning from coverage feedback. Our method biases selection towards tests that have a high probability of increasing functional coverage, and prioritises them for simulation. We show how coverage-directed test selection can reduce manual constraint writing, prioritise effective tests, reduce verification resource consumption, and accelerate coverage closure on a large, real-life industrial hardware design.