# MRAM-based Analog Sigmoid Function for In-memory Computing

arXiv: https://arxiv.org/abs/2204.09918 · HTML: https://mlsanity.com/paper/2204.09918/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- Builds on 6 of its 26 references that are in the map.
- First posted on arXiv 21 Apr 2022.

## Builds on (most cited first, 6 of 6)

- [Very Deep Convolutional Networks for Large-Scale Image Recognition](https://mlsanity.com/paper/1409.1556/) (2014)
- [Going Deeper with Convolutions](https://mlsanity.com/paper/1409.4842/) (2014)
- [PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference](https://mlsanity.com/paper/1901.10351/) (2019)
- [An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices](https://mlsanity.com/paper/2105.13904/) (2021)
- [Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures](https://mlsanity.com/paper/2201.12480/) (2022)
- [Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons](https://mlsanity.com/paper/1811.11390/) (2018)

## Built on by (most cited first, 4 of 4)

- [Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units](https://mlsanity.com/paper/2304.09258/) (2023)
- [IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architectures](https://mlsanity.com/paper/2304.09252/) (2023)
- [PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMs](https://mlsanity.com/paper/2504.01994/) (2025)
- [Reliability-Aware Deployment of DNNs on In-Memory Analog Computing Architectures](https://mlsanity.com/paper/2211.00590/) (2022)

## Abstract (arXiv)

We propose an analog implementation of the transcendental activation function leveraging two spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and a CMOS inverter. The proposed analog neuron circuit consumes 1.8-27x less power, and occupies 2.5-4931x smaller area, compared to the state-of-the-art analog and digital implementations. Moreover, the developed neuron can be readily integrated with memristive crossbars without requiring any intermediate signal conversion units. The architecture-level analyses show that a fully-analog in-memory computing (IMC) circuit that use our SOT-MRAM neuron along with an SOT-MRAM based crossbar can achieve more than 1.1x, 12x, and 13.3x reduction in power, latency, and energy, respectively, compared to a mixed-signal implementation with analog memristive crossbars and digital neurons. Finally, through cross-layer analyses, we provide a guide on how varying the device-level parameters in our neuron can affect the accuracy of multilayer perceptron (MLP) for MNIST classification.