# DT2CAM: A Decision Tree to Content Addressable Memory Framework

arXiv: https://arxiv.org/abs/2204.06114 · HTML: https://mlsanity.com/paper/2204.06114/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 5 of its 44 references that are in the map.
- First posted on arXiv 12 Apr 2022.

## Builds on (most cited first, 5 of 5)

- [Explainable Artificial Intelligence (XAI): Concepts, Taxonomies, Opportunities and Challenges toward Responsible AI](https://mlsanity.com/paper/1910.10045/) (2019)
- [An Explainable Machine Learning Model for Early Detection of Parkinson's Disease using LIME on DaTscan Imagery](https://mlsanity.com/paper/2008.00238/) (2020)
- [In-memory Associative Processors: Tutorial, Potential, and Challenges](https://mlsanity.com/paper/2203.00662/) (2022)
- [Deep Random Forest with Ferroelectric Analog Content Addressable Memory](https://mlsanity.com/paper/2110.02495/) (2021)
- [Efficient Analog CAM Design](https://mlsanity.com/paper/2203.02500/) (2022)

## Abstract (arXiv)

Decision trees are considered one of the most powerful tools for data classification. Accelerating the decision tree search is crucial for on-the-edge applications that have limited power and latency budget. In this paper, we propose a Content Addressable Memory (CAM) Compiler for Decision Tree (DT) inference acceleration. We propose a novel "adaptive-precision" scheme that results in a compact implementation and enables an efficient bijective mapping to Ternary Content Addressable Memories while maintaining high inference accuracies. In addition, a Resistive-CAM (ReCAM) functional synthesizer is developed for mapping the decision tree to the ReCAM and performing functional simulations for energy, latency, and accuracy evaluations. We study the decision tree accuracy under hardware non-idealities including device defects, manufacturing variability, and input encoding noise. We test our framework on various DT datasets including textitGive Me Some Credit, textitTitanic, and textitCOVID-19. Our results reveal up to 42.4% energy savings and up to 17.8x better energy-delay-area product compared to the state-of-art hardware accelerators, and up to 333 million decisions per sec for the pipelined implementation.