# A Design Methodology for Fault-Tolerant Computing using Astrocyte Neural Networks

arXiv: https://arxiv.org/abs/2204.02942 · HTML: https://mlsanity.com/paper/2204.02942/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 6 Apr 2022.

## Built on by (most cited first, 4 of 4)

- [Exploiting FPGA Capabilities for Accelerated Biomedical Computing](https://mlsanity.com/paper/2307.07914/) (2023)
- [NEUROSEC: FPGA-Based Neuromorphic Audio Security](https://mlsanity.com/paper/2401.12055/) (2024)
- [Advancing Neuromorphic Computing: Mixed-Signal Design Techniques Leveraging Brain Code Units and Fundamental Code Units](https://mlsanity.com/paper/2403.11563/) (2024)
- [HPCNeuroNet: A Neuromorphic Approach Merging SNN Temporal Dynamics with Transformer Attention for FPGA-based Particle Physics](https://mlsanity.com/paper/2412.17571/) (2024)

## Abstract (arXiv)

We propose a design methodology to facilitate fault tolerance of deep learning models. First, we implement a many-core fault-tolerant neuromorphic hardware design, where neuron and synapse circuitries in each neuromorphic core are enclosed with astrocyte circuitries, the star-shaped glial cells of the brain that facilitate self-repair by restoring the spike firing frequency of a failed neuron using a closed-loop retrograde feedback signal. Next, we introduce astrocytes in a deep learning model to achieve the required degree of tolerance to hardware faults. Finally, we use a system software to partition the astrocyte-enabled model into clusters and implement them on the proposed fault-tolerant neuromorphic design. We evaluate this design methodology using seven deep learning inference models and show that it is both area and power efficient.