# Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design

arXiv: https://arxiv.org/abs/2203.15913 · HTML: https://mlsanity.com/paper/2203.15913/

## Key facts

- Cited by 13 papers in the map (data through 14 Oct 2026).
- Builds on 13 of its 32 references that are in the map.
- First posted on arXiv 29 Mar 2022.

## Builds on (most cited first, 13 of 13)

- [Semi-Supervised Classification with Graph Convolutional Networks](https://mlsanity.com/paper/1609.02907/) (2016)
- [Graph Attention Networks](https://mlsanity.com/paper/1710.10903/) (2017)
- [Fast Graph Representation Learning with PyTorch Geometric](https://mlsanity.com/paper/1903.02428/) (2019)
- [Open Graph Benchmark: Datasets for Machine Learning on Graphs](https://mlsanity.com/paper/2005.00687/) (2020)
- [Perceiver IO: A General Architecture for Structured Inputs & Outputs](https://mlsanity.com/paper/2107.14795/) (2021)
- [DeeperGCN: All You Need to Train Deeper GCNs](https://mlsanity.com/paper/2006.07739/) (2020)
- [Representing Long-Range Context for Graph Neural Networks with Global Attention](https://mlsanity.com/paper/2201.08821/) (2022)
- [GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2005.00406/) (2020)
- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs](https://mlsanity.com/paper/2001.01808/) (2020)
- [DRiLLS: Deep Reinforcement Learning for Logic Synthesis](https://mlsanity.com/paper/1911.04021/) (2019)
- [BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks](https://mlsanity.com/paper/1907.10515/) (2019)
- [JUMBO: Scalable Multi-task Bayesian Optimization using Offline Data](https://mlsanity.com/paper/2106.00942/) (2021)

## Built on by (most cited first, 13 of 13)

- [CktGNN: Circuit Graph Neural Network for Electronic Design Automation](https://mlsanity.com/paper/2308.16406/) (2023)
- [FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design](https://mlsanity.com/paper/2505.21923/) (2025)
- [Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits](https://mlsanity.com/paper/2312.14405/) (2023)
- [GraCo -- A Graph Composer for Integrated Circuits](https://mlsanity.com/paper/2411.13890/) (2024)
- [DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining](https://mlsanity.com/paper/2502.08949/) (2025)
- [ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings](https://mlsanity.com/paper/2511.07658/) (2025)
- [Circuit Diagram Retrieval Based on Hierarchical Circuit Graph Representation](https://mlsanity.com/paper/2503.11658/) (2025)
- [Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction](https://mlsanity.com/paper/2507.06538/) (2025)
- [AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learning](https://mlsanity.com/paper/2602.12402/) (2026)
- [RF-Informed Graph Neural Networks for Accurate and Data-Efficient Circuit Performance Prediction](https://mlsanity.com/paper/2508.16403/) (2025)
- [GraphPPD: Posterior Predictive Modelling for Graph-Level Inference](https://mlsanity.com/paper/2508.16995/) (2025)
- [SuperCond-GNN: Scalable Graph Neural Network Surrogate for Superconducting Circuit Simulations](https://mlsanity.com/paper/2606.23548/) (2026)
- [cktFormer: Transformer-Based Approach for Automated Analog Circuit Design](https://mlsanity.com/paper/2609.36752/) (2026)

## Abstract (arXiv)

Being able to predict the performance of circuits without running expensive simulations is a desired capability that can catalyze automated design. In this paper, we present a supervised pretraining approach to learn circuit representations that can be adapted to new circuit topologies or unseen prediction tasks. We hypothesize that if we train a neural network (NN) that can predict the output DC voltages of a wide range of circuit instances it will be forced to learn generalizable knowledge about the role of each circuit element and how they interact with each other. The dataset for this supervised learning objective can be easily collected at scale since the required DC simulation to get ground truth labels is relatively cheap. This representation would then be helpful for few-shot generalization to unseen circuit metrics that require more time consuming simulations for obtaining the ground-truth labels. To cope with the variable topological structure of different circuits we describe each circuit as a graph and use graph neural networks (GNNs) to learn node embeddings. We show that pretraining GNNs on prediction of output node voltages can encourage learning representations that can be adapted to new unseen topologies or prediction of new circuit level properties with up to 10x more sample efficiency compared to a randomly initialized model. We further show that we can improve sample efficiency of prior SoTA model-based optimization methods by 2x (almost as good as using an oracle model) via fintuning pretrained GNNs as the feature extractor of the learned models.