# Deep Bidirectional Transformers for SoC Flow Specification Mining

arXiv: https://arxiv.org/abs/2203.13182 · HTML: https://mlsanity.com/paper/2203.13182/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 4 of its 6 references that are in the map.
- First posted on arXiv 9 Mar 2022.

## Builds on (most cited first, 4 of 4)

- [BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding](https://mlsanity.com/paper/1810.04805/) (2018)
- [DistilBERT, a distilled version of BERT: smaller, faster, cheaper and lighter](https://mlsanity.com/paper/1910.01108/) (2019)
- [Mining Message Flows from System-on-Chip Execution Traces](https://mlsanity.com/paper/2005.11221/) (2020)
- [Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs](https://mlsanity.com/paper/2005.01574/) (2020)

## Abstract (arXiv)

High-quality system-level message flow specifications can lead to comprehensive validation of system-on-chip (SoC) designs. We propose a disruptive method that utilizes an attention mechanism to produce accurate flow specifications from SoC IP communication traces. The proposed method can overcome the inherent complexity of SoC traces induced by the concurrency and parallelism of multicore designs that existing flow specification mining tools often find extremely challenging. Experiments on highly interleaved traces show promising flow reconstruction compared to several tools dedicated to the flow specification mining problem.