# DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks

arXiv: https://arxiv.org/abs/2203.11028 · HTML: https://mlsanity.com/paper/2203.11028/

## Key facts

- Cited by 5 papers in the map (data through 14 Oct 2026).
- Builds on 3 of its 14 references that are in the map.
- First posted on arXiv 21 Mar 2022.

## Builds on (most cited first, 3 of 3)

- [Efficient Processing of Deep Neural Networks: A Tutorial and Survey](https://mlsanity.com/paper/1703.09039/) (2017)
- [Spiking Neural Networks Hardware Implementations and Challenges: a Survey](https://mlsanity.com/paper/2005.01467/) (2020)
- [Near-Precise Parameter Approximation for Multiple Multiplications on A Single DSP Block](https://mlsanity.com/paper/2104.02162/) (2021)

## Built on by (most cited first, 5 of 5)

- [BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs](https://mlsanity.com/paper/2304.03974/) (2023)
- [DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs](https://mlsanity.com/paper/2308.11334/) (2023)
- [MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs](https://mlsanity.com/paper/2407.18267/) (2024)
- [Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator](https://mlsanity.com/paper/2408.07404/) (2024)
- [Arithmetic Packing on Wide Integer Datapaths in DSP Primitives of Modern FPGA Devices](https://mlsanity.com/paper/2606.11065/) (2026)

## Abstract (arXiv)

The number of Digital Signal Processor (DSP) resources available in Field Programmable Gate Arrays (FPGAs) is often quite limited. Therefore, full utilization of available DSP resources for the computationally intensive parts of an algorithm is paramount for optimizing the non-functional properties of an implementation (i.e., performance, power, and area). The DSPs available in Xilinx devices implement large bit width operators (i.e. a 48-bit accumulator or a 18 × 27 multiplier). However, using such a DSP for low-precision quantized data (as is common in image processing or machine learning applications) leaves the DSP resources underutilized. As a remedy, A method has been proposed to pack and compute four 4-bit multiplications on a single DSP in a single clock cycle. This paper presents a generalization of this scheme to arbitrary bit widths and number of multiplications. We also demonstrate that the previously proposed approach leads to errors (Mean Absolute Error (MAE) = 0.37). Furthermore, we explain where these errors come from and how they can be corrected. On top, we introduce a novel approximate method called "Overpacking" which allows to squeeze even more multiplications into a single DSP at the cost of small errors (MAE = 0.47). Overpacking allows to squeeze six 4-bit multiplications into a single DSP compared to just four in the literature. Finally, we introduce an alternative method for packing multiple small-bit width additions into a single 48-bit accumulator for use in applications such as Spiking Neural Networks.