# Towards Enabling Dynamic Convolution Neural Network Inference for Edge Intelligence

arXiv: https://arxiv.org/abs/2202.09461 · HTML: https://mlsanity.com/paper/2202.09461/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 7 of its 14 references that are in the map.
- First posted on arXiv 18 Feb 2022.

## Builds on (most cited first, 7 of 7)

- [Edge Intelligence: Paving the Last Mile of Artificial Intelligence with Edge Computing](https://mlsanity.com/paper/1905.10083/) (2019)
- [Convergence of Edge Computing and Deep Learning: A Comprehensive Survey](https://mlsanity.com/paper/1907.08349/) (2019)
- [FPGA-based Accelerators of Deep Learning Networks for Learning and Classification: A Review](https://mlsanity.com/paper/1901.00121/) (2019)
- [SoWaF: Shuffling of Weights and Feature Maps: A Novel Hardware Intrinsic Attack (HIA) on Convolutional Neural Network (CNN)](https://mlsanity.com/paper/2103.09327/) (2021)
- [MAFAT: Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference](https://mlsanity.com/paper/2107.06960/) (2021)
- [FeSHI: Feature Map Based Stealthy Hardware Intrinsic Attack](https://mlsanity.com/paper/2106.06895/) (2021)
- [Security Analysis of Capsule Network Inference using Horizontal Collaboration](https://mlsanity.com/paper/2109.11041/) (2021)

## Abstract (arXiv)

Deep learning applications have achieved great success in numerous real-world applications. Deep learning models, especially Convolution Neural Networks (CNN) are often prototyped using FPGA because it offers high power efficiency and reconfigurability. The deployment of CNNs on FPGAs follows a design cycle that requires saving of model parameters in the on-chip memory during High-level synthesis (HLS). Recent advances in edge intelligence require CNN inference on edge network to increase throughput and reduce latency. To provide flexibility, dynamic parameter allocation to different mobile devices is required to implement either a predefined or defined on-the-fly CNN architecture. In this study, we present novel methodologies for dynamically streaming the model parameters at run-time to implement a traditional CNN architecture. We further propose a library-based approach to design scalable and dynamic distributed CNN inference on the fly leveraging partial-reconfiguration techniques, which is particularly suitable for resource-constrained edge devices. The proposed techniques are implemented on the Xilinx PYNQ-Z2 board to prove the concept by utilizing the LeNet-5 CNN model. The results show that the proposed methodologies are effective, with classification accuracy rates of 92%, 86%, and 94% respectively