# SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators

arXiv: https://arxiv.org/abs/2202.08395 · HTML: https://mlsanity.com/paper/2202.08395/

## Key facts

- Cited by 16 papers in the map (data through 14 Oct 2026).
- Builds on 6 of its 13 references that are in the map.
- First posted on arXiv 17 Feb 2022.

## Builds on (most cited first, 6 of 6)

- [Deep Residual Learning for Image Recognition](https://mlsanity.com/paper/1512.03385/) (2015)
- [Efficient Processing of Deep Neural Networks: A Tutorial and Survey](https://mlsanity.com/paper/1703.09039/) (2017)
- [Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators](https://mlsanity.com/paper/1911.00139/) (2019)
- [Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search](https://mlsanity.com/paper/2107.06871/) (2021)
- [When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies](https://mlsanity.com/paper/1909.04697/) (2019)
- [RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search](https://mlsanity.com/paper/2109.05691/) (2021)

## Built on by (most cited first, 16 of 16)

- [Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?](https://mlsanity.com/paper/2207.07626/) (2022)
- [Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures](https://mlsanity.com/paper/2405.04700/) (2024)
- [On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators](https://mlsanity.com/paper/2306.06923/) (2023)
- [FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models](https://mlsanity.com/paper/2402.06696/) (2024)
- [Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise](https://mlsanity.com/paper/2307.15853/) (2023)
- [Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections](https://mlsanity.com/paper/2312.06137/) (2023)
- [TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators](https://mlsanity.com/paper/2406.06544/) (2024)
- [NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Accelerators](https://mlsanity.com/paper/2305.14561/) (2023)
- [Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAM](https://mlsanity.com/paper/2401.11664/) (2024)
- [HaLoRA: Hardware-aware Low-Rank Adaptation for Large Language Models Based on Hybrid Compute-in-Memory Architecture](https://mlsanity.com/paper/2502.19747/) (2025)
- [TinyML Design Contest for Life-Threatening Ventricular Arrhythmia Detection](https://mlsanity.com/paper/2305.05105/) (2023)
- [When Small Variations Become Big Failures: Reliability Challenges in Compute-in-Memory Neural Accelerators](https://mlsanity.com/paper/2603.03491/) (2026)
- [U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators](https://mlsanity.com/paper/2401.05357/) (2023)
- [FedLAM: Low-latency Wireless Federated Learning via Layer-wise Adaptive Modulation](https://mlsanity.com/paper/2510.07766/) (2025)
- [CiMRAG: CiM-Aware Domain-Adaptive and Noise-Resilient Retrieval-Augmented Generation for Edge-Based LLMs](https://mlsanity.com/paper/2601.20041/) (2026)
- [Interface-Aware KV Cache Quantization for Dense On-Chip NVM in Long-Context LLM Decoding](https://mlsanity.com/paper/2609.05764/) (2026)

## Abstract (arXiv)

Computing-in-Memory architectures based on non-volatile emerging memories have demonstrated great potential for deep neural network (DNN) acceleration thanks to their high energy efficiency. However, these emerging devices can suffer from significant variations during the mapping process i.e., programming weights to the devices), and if left undealt with, can cause significant accuracy degradation. The non-ideality of weight mapping can be compensated by iterative programming with a write-verify scheme, i.e., reading the conductance and rewriting if necessary. In all existing works, such a practice is applied to every single weight of a DNN as it is being mapped, which requires extensive programming time. In this work, we show that it is only necessary to select a small portion of the weights for write-verify to maintain the DNN accuracy, thus achieving significant speedup. We further introduce a second derivative based technique SWIM, which only requires a single pass of forward and backpropagation, to efficiently select the weights that need write-verify. Experimental results on various DNN architectures for different datasets show that SWIM can achieve up to 10x programming speedup compared with conventional full-blown write-verify while attaining a comparable accuracy.