# FlowTune: End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit

arXiv: https://arxiv.org/abs/2202.07721 · HTML: https://mlsanity.com/paper/2202.07721/

## Key facts

- Cited by 11 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 15 Feb 2022.

## Built on by (most cited first, 11 of 11)

- [Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization](https://mlsanity.com/paper/2401.12205/) (2024)
- [MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization](https://mlsanity.com/paper/2507.19570/) (2025)
- [Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC](https://mlsanity.com/paper/2604.15082/) (2026)
- [Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs](https://mlsanity.com/paper/2311.05722/) (2023)
- [INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search](https://mlsanity.com/paper/2305.13164/) (2023)
- [BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation](https://mlsanity.com/paper/2401.10753/) (2024)
- [MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization](https://mlsanity.com/paper/2409.06077/) (2024)
- [e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving](https://mlsanity.com/paper/2508.13020/) (2025)
- [SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR](https://mlsanity.com/paper/2308.07654/) (2023)
- [Rethinking Logic Optimization Operators: Theory-Derived Operator Compression via Agentic Source Analysis](https://mlsanity.com/paper/2607.23672/) (2026)
- [LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation](https://mlsanity.com/paper/2610.16625/) (2026)

## Abstract (arXiv)

Recent years have seen increasing employment of decision intelligence in electronic design automation (EDA), which aims to reduce the manual efforts and boost the design closure process in modern toolflows. However, existing approaches either require a large number of labeled data and expensive training efforts, or are limited in practical EDA toolflow integration due to computation overhead. This paper presents a generic end-to-end sequential decision making framework FlowTune for synthesis tooflow optimization, with a novel high-performance domain-specific, multi-stage multi-armed bandit (MAB) approach. This framework addresses optimization problems on Boolean optimization problems such as a) And-Inv-Graphs (# nodes), b) Conjunction Normal Form (CNF) minimization (# clauses) for Boolean Satisfiability; logic synthesis and technology mapping problems such as c) post static timing analysis (STA) delay and area optimization for standard-cell technology mapping, and d) FPGA technology mapping for 6-in LUT architectures. Moreover, we demonstrate the high extnsibility and generalizability of the proposed domain-specific MAB approach with end-to-end FPGA design flow, evaluated at post-routing stage, with two different FPGA backend tools (OpenFPGA and VPR) and two different logic synthesis representations (AIGs and MIGs). FlowTune is fully integrated with ABC [1], Yosys [2], VTR [3], LSOracle [4], OpenFPGA [5], and industrial tools, and is released publicly. The experimental results conducted on various design stages in the flow all demonstrate that our framework outperforms both hand-crafted flows [1] and ML explored flows [6], [7] in quality of results, and is orders of magnitude faster compared to ML-based approaches.