# A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm with 0.1-nA PTAT and 1.1-μA CWT 38-ppm/^circC Designs

arXiv: https://arxiv.org/abs/2202.01751 · HTML: https://mlsanity.com/paper/2202.01751/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 3 Feb 2022.

## Built on by (most cited first, 1 of 1)

- [IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping](https://mlsanity.com/paper/2412.19750/) (2024)

## Abstract (arXiv)

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18-μm partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant-gm biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/^circC, and a variability (σ/μ) of 1.66 %. Then, two 4T+1R μA-range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09-μA (resp. 0.99-μA) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/^circC (resp. 290-ppm/^circC) TC, and a 0.87-% (resp. 0.65-%) (σ/μ). In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations.