# Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures

arXiv: https://arxiv.org/abs/2201.12480 · HTML: https://mlsanity.com/paper/2201.12480/

## Key facts

- Cited by 6 papers in the map (data through 14 Oct 2026).
- Builds on 3 of its 23 references that are in the map.
- First posted on arXiv 29 Jan 2022.

## Builds on (most cited first, 3 of 3)

- [PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference](https://mlsanity.com/paper/1901.10351/) (2019)
- [High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS](https://mlsanity.com/paper/1909.07514/) (2019)
- [An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices](https://mlsanity.com/paper/2105.13904/) (2021)

## Built on by (most cited first, 6 of 6)

- [MRAM-based Analog Sigmoid Function for In-memory Computing](https://mlsanity.com/paper/2204.09918/) (2022)
- [Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units](https://mlsanity.com/paper/2304.09258/) (2023)
- [IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architectures](https://mlsanity.com/paper/2304.09252/) (2023)
- [Multi-Objective Neural Architecture Search for In-Memory Computing](https://mlsanity.com/paper/2406.06746/) (2024)
- [Reliability-Aware Deployment of DNNs on In-Memory Analog Computing Architectures](https://mlsanity.com/paper/2211.00590/) (2022)
- [CrossNAS: A Cross-Layer Neural Architecture Search Framework for PIM Systems](https://mlsanity.com/paper/2505.22868/) (2025)

## Abstract (arXiv)

Fully-analog in-memory computing (IMC) architectures that implement both matrix-vector multiplication and non-linear vector operations within the same memory array have shown promising performance benefits over conventional IMC systems due to the removal of energy-hungry signal conversion units. However, maintaining the computation in the analog domain for the entire deep neural network (DNN) comes with potential sensitivity to interconnect parasitics. Thus, in this paper, we investigate the effect of wire parasitic resistance and capacitance on the accuracy of DNN models deployed on fully-analog IMC architectures. Moreover, we propose a partitioning mechanism to alleviate the impact of the parasitic while keeping the computation in the analog domain through dividing large arrays into multiple partitions. The SPICE circuit simulation results for a 400 X 120 X 84 X 10 DNN model deployed on a fully-analog IMC circuit show that a 94.84% accuracy could be achieved for MNIST classification application with 16, 8, and 8 horizontal partitions, as well as 8, 8, and 1 vertical partitions for first, second, and third layers of the DNN, respectively, which is comparable to the ~97% accuracy realized by digital implementation on CPU. It is shown that accuracy benefits are achieved at the cost of higher power consumption due to the extra circuitry required for handling partitioning.