# Puppeteer: A Random Forest-based Manager for Hardware Prefetchers across the Memory Hierarchy

arXiv: https://arxiv.org/abs/2201.12027 · HTML: https://mlsanity.com/paper/2201.12027/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 5 of its 79 references that are in the map.
- First posted on arXiv 28 Jan 2022.

## Builds on (most cited first, 5 of 5)

- [Learning Memory Access Patterns](https://mlsanity.com/paper/1803.02329/) (2018)
- [Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning](https://mlsanity.com/paper/2109.12021/) (2021)
- [Robustness of Random Forest-based gene selection methods](https://mlsanity.com/paper/1305.4525/) (2013)
- [A neural network memory prefetcher using semantic locality](https://mlsanity.com/paper/1804.00478/) (2018)
- [Using Grouped Linear Prediction and Accelerated Reinforcement Learning for Online Content Caching](https://mlsanity.com/paper/1803.04675/) (2018)

## Built on by (most cited first, 2 of 2)

- [Attention, Distillation, and Tabularization: Towards Practical Neural Network-Based Prefetching](https://mlsanity.com/paper/2401.06362/) (2023)
- [Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning](https://mlsanity.com/paper/2601.17615/) (2026)

## Abstract (arXiv)

Over the years, processor throughput has steadily increased. However, the memory throughput has not increased at the same rate, which has led to the memory wall problem in turn increasing the gap between effective and theoretical peak processor performance. To cope with this, there has been an abundance of work in the area of data/instruction prefetcher designs. Broadly, prefetchers predict future data/instruction address accesses and proactively fetch data/instructions in the memory hierarchy with the goal of lowering data/instruction access latency. To this end, one or more prefetchers are deployed at each level of the memory hierarchy, but typically, each prefetcher gets designed in isolation without comprehensively accounting for other prefetchers in the system. As a result, individual prefetchers do not always complement each other, and that leads to lower average performance gains and/or many negative outliers. In this work, we propose Puppeteer, which is a hardware prefetcher manager that uses a suite of random forest regressors to determine at runtime which prefetcher should be ON at each level in the memory hierarchy, such that the prefetchers complement each other and we reduce the data/instruction access latency. Compared to a design with no prefetchers, using Puppeteer we improve IPC by 46.0% in 1 Core (1C), 25.8% in 4 Core (4C), and 11.9% in 8 Core (8C) processors on average across traces generated from SPEC2017, SPEC2006, and Cloud suites with ~10KB overhead. Moreover, we also reduce the number of negative outliers by over 89%, and the performance loss of the worst-case negative outlier from 25% to only 5% compared to the state-of-the-art.