# LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models

arXiv: https://arxiv.org/abs/2201.08455 · HTML: https://mlsanity.com/paper/2201.08455/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- Builds on 15 of its 38 references that are in the map.
- First posted on arXiv 20 Jan 2022.

## Builds on (most cited first, 15 of 15)

- [PyTorch: An Imperative Style, High-Performance Deep Learning Library](https://mlsanity.com/paper/1912.01703/) (2019)
- [Semi-Supervised Classification with Graph Convolutional Networks](https://mlsanity.com/paper/1609.02907/) (2016)
- [How Powerful are Graph Neural Networks?](https://mlsanity.com/paper/1810.00826/) (2018)
- [Neural Message Passing for Quantum Chemistry](https://mlsanity.com/paper/1704.01212/) (2017)
- [Fast Graph Representation Learning with PyTorch Geometric](https://mlsanity.com/paper/1903.02428/) (2019)
- [Graph Neural Networks for Social Recommendation](https://mlsanity.com/paper/1902.07243/) (2019)
- [Provably Powerful Graph Networks](https://mlsanity.com/paper/1905.11136/) (2019)
- [Towards Deeper Graph Neural Networks](https://mlsanity.com/paper/2007.09296/) (2020)
- [A Survey of Machine Learning for Computer Architecture and Systems](https://mlsanity.com/paper/2102.07952/) (2021)
- [DRiLLS: Deep Reinforcement Learning for Logic Synthesis](https://mlsanity.com/paper/1911.04021/) (2019)
- [Few-Shot Representation Learning for Out-Of-Vocabulary Words](https://mlsanity.com/paper/1907.00505/) (2019)
- [Developing Synthesis Flows Without Human Knowledge](https://mlsanity.com/paper/1804.05714/) (2018)
- [IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning](https://mlsanity.com/paper/2102.08138/) (2021)
- [High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing](https://mlsanity.com/paper/2201.06848/) (2022)
- [Standard Cell Library Design and Optimization Methodology for ASAP7 PDK](https://mlsanity.com/paper/1807.11396/) (2018)

## Built on by (most cited first, 7 of 7)

- [Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs](https://mlsanity.com/paper/2311.05722/) (2023)
- [Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs](https://mlsanity.com/paper/2211.16495/) (2022)
- [ShortCircuit: AlphaZero-Driven Circuit Design](https://mlsanity.com/paper/2408.09858/) (2024)
- [MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization](https://mlsanity.com/paper/2409.06077/) (2024)
- [Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers](https://mlsanity.com/paper/2409.10653/) (2024)
- [A Benchmark on Directed Graph Representation Learning in Hardware Designs](https://mlsanity.com/paper/2410.06460/) (2024)
- [BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction](https://mlsanity.com/paper/2511.02196/) (2025)

## Abstract (arXiv)

Despite the stride made by machine learning (ML) based performance modeling, two major concerns that may impede production-ready ML applications in EDA are stringent accuracy requirements and generalization capability. To this end, we propose hybrid graph neural network (GNN) based approaches towards highly accurate quality-of-result (QoR) estimations with great generalization capability, specifically targeting logic synthesis optimization. The key idea is to simultaneously leverage spatio-temporal information from hardware designs and logic synthesis flows to forecast performance (i.e., delay/area) of various synthesis flows on different designs. The structural characteristics inside hardware designs are distilled and represented by GNNs; the temporal knowledge (i.e., relative ordering of logic transformations) in synthesis flows can be imposed on hardware designs by combining a virtually added supernode or a sequence processing model with conventional GNN models. Evaluation on 3.3 million data points shows that the testing mean absolute percentage error (MAPE) on designs seen and unseen during training are no more than 1.2% and 3.1%, respectively, which are 7-15X lower than existing studies.