# Spiker: an FPGA-optimized Hardware acceleration for Spiking Neural Networks

arXiv: https://arxiv.org/abs/2201.06993 · HTML: https://mlsanity.com/paper/2201.06993/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- Builds on 1 of its 29 references that are in the map.
- First posted on arXiv 18 Jan 2022.

## Builds on (most cited first, 1 of 1)

- [FSpiNN: An Optimization Framework for Memory- and Energy-Efficient Spiking Neural Networks](https://mlsanity.com/paper/2007.08860/) (2020)

## Built on by (most cited first, 8 of 8)

- [Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge](https://mlsanity.com/paper/2401.01141/) (2024)
- [A Fully-Configurable Open-Source Software-Defined Digital Quantized Spiking Neural Core Architecture](https://mlsanity.com/paper/2404.02248/) (2024)
- [SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA](https://mlsanity.com/paper/2404.03714/) (2024)
- [Improving Performance of Spike-based Deep Q-Learning using Ternary Neurons](https://mlsanity.com/paper/2506.03392/) (2025)
- [Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking Neurons](https://mlsanity.com/paper/2506.13268/) (2025)
- [SpikingJET: Enhancing Fault Injection for Fully and Convolutional Spiking Neural Networks](https://mlsanity.com/paper/2404.00383/) (2024)
- [An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks](https://mlsanity.com/paper/2603.18054/) (2026)
- [Spiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks](https://mlsanity.com/paper/2605.18003/) (2026)

## Abstract (arXiv)

Spiking Neural Networks (SNN) are an emerging type of biologically plausible and efficient Artificial Neural Network (ANN). This work presents the development of a hardware accelerator for a SNN for high-performance inference, targeting a Xilinx Artix-7 Field Programmable Gate Array (FPGA). The model used inside the neuron is the Leaky Integrate and Fire (LIF). The execution is clock-driven, meaning that the internal state of the neuron is updated at every clock cycle, even in absence of spikes. The inference capabilities of the accelerator are evaluated using the MINST dataset. The training is performed offline on a full precision model. The results show a good improvement in performance if compared with the state-of-the-art accelerators, requiring 215μs per image. The energy consumption is slightly higher than the most optimized design, with an average value of 13mJ per image. The test design consists of a single layer of four-hundred neurons and uses around 40% of the available resources on the FPGA. This makes it suitable for a time-constrained application at the edge, leaving space for other acceleration tasks on the FPGA.