# CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs

arXiv: https://arxiv.org/abs/2201.01863 · HTML: https://mlsanity.com/paper/2201.01863/

## Key facts

- Cited by 11 papers in the map (data through 14 Oct 2026).
- Builds on 14 of its 39 references that are in the map.
- First posted on arXiv 5 Jan 2022.

## Builds on (most cited first, 14 of 14)

- [TensorFlow Lite Micro: Embedded Machine Learning on TinyML Systems](https://mlsanity.com/paper/2010.08678/) (2020)
- [The Hardware Lottery](https://mlsanity.com/paper/2009.06489/) (2020)
- [FINN: A Framework for Fast, Scalable Binarized Neural Network Inference](https://mlsanity.com/paper/1612.07119/) (2016)
- [MLPerf Tiny Benchmark](https://mlsanity.com/paper/2106.07597/) (2021)
- [CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs](https://mlsanity.com/paper/1801.06601/) (2018)
- [Benchmarking TinyML Systems: Challenges and Direction](https://mlsanity.com/paper/2003.04821/) (2020)
- [Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration](https://mlsanity.com/paper/1911.09925/) (2019)
- [hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices](https://mlsanity.com/paper/2103.05579/) (2021)
- [FPGA-based Accelerators of Deep Learning Networks for Learning and Classification: A Review](https://mlsanity.com/paper/1901.00121/) (2019)
- [Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions](https://mlsanity.com/paper/1803.05900/) (2018)
- [Agile SoC Development with Open ESP](https://mlsanity.com/paper/2009.01178/) (2020)
- [LiteX: an open-source SoC builder and library based on Migen Python DSL](https://mlsanity.com/paper/2005.02506/) (2020)
- [AI Tax: The Hidden Cost of AI Data Center Applications](https://mlsanity.com/paper/2007.10571/) (2020)
- [Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs](https://mlsanity.com/paper/1903.10407/) (2019)

## Built on by (most cited first, 11 of 11)

- [A Machine Learning-oriented Survey on Tiny Machine Learning](https://mlsanity.com/paper/2309.11932/) (2023)
- [Edge Impulse: An MLOps Platform for Tiny Machine Learning](https://mlsanity.com/paper/2212.03332/) (2022)
- [Chameleon: a Heterogeneous and Disaggregated Accelerator System for Retrieval-Augmented Language Models](https://mlsanity.com/paper/2310.09949/) (2023)
- [Tiny Robot Learning: Challenges and Directions for Machine Learning in Resource-Constrained Robots](https://mlsanity.com/paper/2205.05748/) (2022)
- [Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits](https://mlsanity.com/paper/2302.14576/) (2023)
- [Machine Learning Sensors](https://mlsanity.com/paper/2206.03266/) (2022)
- [Designing Object Detection Models for TinyML: Foundations, Comparative Analysis, Challenges, and Emerging Solutions](https://mlsanity.com/paper/2508.08352/) (2025)
- [RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI](https://mlsanity.com/paper/2511.21232/) (2025)
- [AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming](https://mlsanity.com/paper/2309.13445/) (2023)
- [Accelerating TinyML Inference on Microcontrollers through Approximate Kernels](https://mlsanity.com/paper/2409.16815/) (2024)
- [Lifetime-Aware Design for Item-Level Intelligence at the Extreme Edge](https://mlsanity.com/paper/2509.08193/) (2025)

## Abstract (arXiv)

Need for the efficient processing of neural networks has given rise to the development of hardware accelerators. The increased adoption of specialized hardware has highlighted the need for more agile design flows for hardware-software co-design and domain-specific optimizations. In this paper, we present CFU Playground: a full-stack open-source framework that enables rapid and iterative design and evaluation of machine learning (ML) accelerators for embedded ML systems. Our tool provides a completely open-source end-to-end flow for hardware-software co-design on FPGAs and future systems research. This full-stack framework gives the users access to explore experimental and bespoke architectures that are customized and co-optimized for embedded ML. Our rapid, deploy-profile-optimization feedback loop lets ML hardware and software developers achieve significant returns out of a relatively small investment in customization. Using CFU Playground's design and evaluation loop, we show substantial speedups between 55× and 75×. The soft CPU coupled with the accelerator opens up a new, rich design space between the two components that we explore in an automated fashion using Vizier, an open-source black-box optimization service.