# E3NE: An End-to-End Framework for Accelerating Spiking Neural Networks with Emerging Neural Encoding on FPGAs

arXiv: https://arxiv.org/abs/2111.10027 · HTML: https://mlsanity.com/paper/2111.10027/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 19 Nov 2021.

## Built on by (most cited first, 8 of 8)

- [Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge](https://mlsanity.com/paper/2401.01141/) (2024)
- [DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs](https://mlsanity.com/paper/2305.05187/) (2023)
- [A Resource-efficient Spiking Neural Network Accelerator Supporting Emerging Neural Encoding](https://mlsanity.com/paper/2206.02495/) (2022)
- [SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA](https://mlsanity.com/paper/2404.03714/) (2024)
- [FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration with Reconfigurable Spatial Architecture](https://mlsanity.com/paper/2408.15578/) (2024)
- [SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST](https://mlsanity.com/paper/2507.10561/) (2025)
- [Desire Backpropagation: A Lightweight Training Algorithm for Multi-Layer Spiking Neural Networks based on Spike-Timing-Dependent Plasticity](https://mlsanity.com/paper/2211.05412/) (2022)
- [Syn2Logic: End-to-End Neuromorphic Design Automation](https://mlsanity.com/paper/2608.25536/) (2026)

## Abstract (arXiv)

Compiler frameworks are crucial for the widespread use of FPGA-based deep learning accelerators. They allow researchers and developers, who are not familiar with hardware engineering, to harness the performance attained by domain-specific logic. There exists a variety of frameworks for conventional artificial neural networks. However, not much research effort has been put into the creation of frameworks optimized for spiking neural networks (SNNs). This new generation of neural networks becomes increasingly interesting for the deployment of AI on edge devices, which have tight power and resource constraints. Our end-to-end framework E3NE automates the generation of efficient SNN inference logic for FPGAs. Based on a PyTorch model and user parameters, it applies various optimizations and assesses trade-offs inherent to spike-based accelerators. Multiple levels of parallelism and the use of an emerging neural encoding scheme result in an efficiency superior to previous SNN hardware implementations. For a similar model, E3NE uses less than 50% of hardware resources and 20% less power, while reducing the latency by an order of magnitude. Furthermore, scalability and generality allowed the deployment of the large-scale SNN models AlexNet and VGG.