# Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding

arXiv: https://arxiv.org/abs/2111.08920 · HTML: https://mlsanity.com/paper/2111.08920/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 4 of its 38 references that are in the map.
- First posted on arXiv 17 Nov 2021.

## Builds on (most cited first, 4 of 4)

- [Information Bottleneck Decoding of Rate-Compatible 5G-LDPC Codes](https://mlsanity.com/paper/1906.08985/) (2019)
- [A Reconstruction-Computation-Quantization (RCQ) Approach to Node Operations in LDPC Decoding](https://mlsanity.com/paper/2005.07259/) (2020)
- [A 588 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing](https://mlsanity.com/paper/1703.05769/) (2017)
- [FPGA Implementations of Layered MinSum LDPC Decoders Using RCQ Message Passing](https://mlsanity.com/paper/2104.09480/) (2021)

## Abstract (arXiv)

This paper uses the reconstruction-computation-quantization (RCQ) paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution (DDE). Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding MinSum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ (LS-RCQ), an extension of RCQ decoding for layered architectures. LS-RCQ uses layer-specific message representations to achieve the best possible FER performance. For LS-RCQ, this paper proposes using layered DDE featuring hierarchical dynamic quantization (HDQ) to design LS-RCQ parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered MinSum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset MinSum decoder.