# On Joint Learning for Solving Placement and Routing in Chip Design

arXiv: https://arxiv.org/abs/2111.00234 · HTML: https://mlsanity.com/paper/2111.00234/

## Key facts

- Cited by 44 papers in the map (data through 14 Oct 2026).
- Builds on 8 of its 34 references that are in the map.
- First posted on arXiv 30 Oct 2021.

## Builds on (most cited first, 8 of 8)

- [Adam: A Method for Stochastic Optimization](https://mlsanity.com/paper/1412.6980/) (2014)
- [PyTorch: An Imperative Style, High-Performance Deep Learning Library](https://mlsanity.com/paper/1912.01703/) (2019)
- [Proximal Policy Optimization Algorithms](https://mlsanity.com/paper/1707.06347/) (2017)
- [Semi-Supervised Classification with Graph Convolutional Networks](https://mlsanity.com/paper/1609.02907/) (2016)
- [Exploration by Random Network Distillation](https://mlsanity.com/paper/1810.12894/) (2018)
- [A Deep Reinforcement Learning Approach for Global Routing](https://mlsanity.com/paper/1906.08809/) (2019)
- [Placement in Integrated Circuits using Cyclic Reinforcement Learning and Simulated Annealing](https://mlsanity.com/paper/2011.07577/) (2020)
- [Attention Routing: track-assignment detailed routing using attention-based reinforcement learning](https://mlsanity.com/paper/2004.09473/) (2020)

## Built on by (most cited first, 30 of 44)

- [SGFormer: Simplifying and Empowering Transformers for Large-Graph Representations](https://mlsanity.com/paper/2306.10759/) (2023)
- [Simulation-guided Beam Search for Neural Combinatorial Optimization](https://mlsanity.com/paper/2207.06190/) (2022)
- [RL4CO: an Extensive Reinforcement Learning for Combinatorial Optimization Benchmark](https://mlsanity.com/paper/2306.17100/) (2023)
- [MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning](https://mlsanity.com/paper/2211.13382/) (2022)
- [ChiPFormer: Transferable Chip Placement via Offline Decision Transformer](https://mlsanity.com/paper/2306.14744/) (2023)
- [LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation](https://mlsanity.com/paper/2401.12224/) (2023)
- [Macro Placement by Wire-Mask-Guided Black-Box Optimization](https://mlsanity.com/paper/2306.16844/) (2023)
- [Machine Learning Methods in Solving the Boolean Satisfiability Problem](https://mlsanity.com/paper/2203.04755/) (2022)
- [Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms](https://mlsanity.com/paper/2407.15026/) (2024)
- [DevFormer: A Symmetric Transformer for Context-Aware Device Placement](https://mlsanity.com/paper/2205.13225/) (2022)
- [An Updated Assessment of Reinforcement Learning for Macro Placement](https://mlsanity.com/paper/2302.11014/) (2023)
- [Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge](https://mlsanity.com/paper/2402.01728/) (2024)
- [Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer](https://mlsanity.com/paper/2412.07167/) (2024)
- [Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs](https://mlsanity.com/paper/2405.06758/) (2024)
- [Evolution of Optimization Algorithms for Global Placement via Large Language Models](https://mlsanity.com/paper/2504.17801/) (2025)
- [PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling](https://mlsanity.com/paper/2403.00012/) (2024)
- [Chip Placement with Diffusion Models](https://mlsanity.com/paper/2407.12282/) (2024)
- [That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design](https://mlsanity.com/paper/2411.10053/) (2024)
- [Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2411.15212/) (2024)
- [BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement](https://mlsanity.com/paper/2510.23472/) (2025)
- [Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview](https://mlsanity.com/paper/2202.13564/) (2022)
- [Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs](https://mlsanity.com/paper/2211.16495/) (2022)
- [Hidden-Variables Genetic Algorithm for Variable-Size Design Space Optimal Layout Problems with Application to Aerospace Vehicles](https://mlsanity.com/paper/2212.11011/) (2022)
- [Toward Reinforcement Learning-based Rectilinear Macro Placement Under Human Constraints](https://mlsanity.com/paper/2311.03383/) (2023)
- [An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design](https://mlsanity.com/paper/2210.15765/) (2022)
- [RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Network](https://mlsanity.com/paper/2406.02651/) (2024)
- [Non-Overlapping Placement of Macro Cells based on Reinforcement Learning in Chip Design](https://mlsanity.com/paper/2407.18499/) (2024)
- [The Power of Graph Signal Processing for Chip Placement Acceleration](https://mlsanity.com/paper/2502.17632/) (2025)
- [Graph Neural Networks for Automatic Addition of Optimizing Components in Printed Circuit Board Schematics](https://mlsanity.com/paper/2506.10577/) (2025)
- [DR-CircuitGNN: Training Acceleration of Heterogeneous Circuit Graph Neural Network on GPUs](https://mlsanity.com/paper/2508.16769/) (2025)

## Abstract (arXiv)

For its advantage in GPU acceleration and less dependency on human experts, machine learning has been an emerging tool for solving the placement and routing problems, as two critical steps in modern chip design flow. Being still in its early stage, there are fundamental issues: scalability, reward design, and end-to-end learning paradigm etc. To achieve end-to-end placement learning, we first propose a joint learning method termed by DeepPlace for the placement of macros and standard cells, by the integration of reinforcement learning with a gradient based optimization scheme. To further bridge the placement with the subsequent routing task, we also develop a joint learning approach via reinforcement learning to fulfill both macro placement and routing, which is called DeepPR. One key design in our (reinforcement) learning paradigm involves a multi-view embedding model to encode both global graph level and local node level information of the input macros. Moreover, the random network distillation is devised to encourage exploration. Experiments on public chip design benchmarks show that our method can effectively learn from experience and also provides intermediate placement for the post standard cell placement, within few hours for training.