# Exploring eFPGA-based Redaction for IP Protection

arXiv: https://arxiv.org/abs/2110.13346 · HTML: https://mlsanity.com/paper/2110.13346/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 26 Oct 2021.

## Built on by (most cited first, 1 of 1)

- [A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation](https://mlsanity.com/paper/2204.09579/) (2022)

## Abstract (arXiv)

Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore functionality by loading the withheld bitstream after fabrication. However, when deciding which parts of a design to redact, there are a number of practical issues that designers need to consider, including area and timing overheads, as well as security factors. Adapting an open-source FPGA fabric generation flow, we perform a case study to explore the trade-offs when redacting different modules of open-source intellectual property blocks (IPs) and explore how different parts of an eFPGA contribute to the security. We provide new insights into the feasibility and challenges of using eFPGA-based redaction as a security solution.