# OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis

arXiv: https://arxiv.org/abs/2110.11292 · HTML: https://mlsanity.com/paper/2110.11292/

## Key facts

- Cited by 30 papers in the map (data through 14 Oct 2026).
- Builds on 4 of its 38 references that are in the map.
- First posted on arXiv 21 Oct 2021.

## Builds on (most cited first, 4 of 4)

- [GLUE: A Multi-Task Benchmark and Analysis Platform for Natural Language Understanding](https://mlsanity.com/paper/1804.07461/) (2018)
- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [DRiLLS: Deep Reinforcement Learning for Logic Synthesis](https://mlsanity.com/paper/1911.04021/) (2019)
- [Developing Synthesis Flows Without Human Knowledge](https://mlsanity.com/paper/1804.05714/) (2018)

## Built on by (most cited first, 30 of 30)

- [End-to-End Meta-Bayesian Optimisation with Transformer Neural Processes](https://mlsanity.com/paper/2305.15930/) (2023)
- [Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms](https://mlsanity.com/paper/2407.15026/) (2024)
- [ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model](https://mlsanity.com/paper/2504.14560/) (2025)
- [DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale](https://mlsanity.com/paper/2502.01681/) (2025)
- [Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization](https://mlsanity.com/paper/2401.12205/) (2024)
- [Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment](https://mlsanity.com/paper/2502.12732/) (2025)
- [HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis](https://mlsanity.com/paper/2302.10977/) (2023)
- [INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search](https://mlsanity.com/paper/2305.13164/) (2023)
- [The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation](https://mlsanity.com/paper/2411.00843/) (2024)
- [OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis](https://mlsanity.com/paper/2411.09422/) (2024)
- [VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code](https://mlsanity.com/paper/2506.07239/) (2025)
- [EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research](https://mlsanity.com/paper/2312.01674/) (2023)
- [MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization](https://mlsanity.com/paper/2409.06077/) (2024)
- [Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis](https://mlsanity.com/paper/2204.02368/) (2022)
- [The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networks](https://mlsanity.com/paper/2207.11437/) (2022)
- [Neural Combinatorial Logic Circuit Synthesis from Input-Output Examples](https://mlsanity.com/paper/2210.16606/) (2022)
- [Towards the Imagenets of ML4EDA](https://mlsanity.com/paper/2310.10560/) (2023)
- [The Seeker's Dilemma: Realistic Formulation and Benchmarking for Hardware Trojan Detection](https://mlsanity.com/paper/2402.17918/) (2024)
- [Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers](https://mlsanity.com/paper/2409.10653/) (2024)
- [A Benchmark on Directed Graph Representation Learning in Hardware Designs](https://mlsanity.com/paper/2410.06460/) (2024)
- [Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network](https://mlsanity.com/paper/2411.10481/) (2024)
- [Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism](https://mlsanity.com/paper/2505.21988/) (2025)
- [FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks](https://mlsanity.com/paper/2506.06787/) (2025)
- [R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII](https://mlsanity.com/paper/2604.08810/) (2026)
- [CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction](https://mlsanity.com/paper/2604.11202/) (2026)
- [Hiding in Plain Sight: Reframing Hardware Trojan Benchmarking as a Hide&Seek Modification](https://mlsanity.com/paper/2410.15550/) (2024)
- [BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction](https://mlsanity.com/paper/2511.02196/) (2025)
- [GSR-GNN: Training Acceleration and Memory-Saving Framework of Deep GNNs on Circuit Graph](https://mlsanity.com/paper/2603.27156/) (2026)
- [CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs](https://mlsanity.com/paper/2610.09549/) (2026)
- [When Algorithmic Exploration Becomes Cheap: A Case Study of Agentic Research in EDA](https://mlsanity.com/paper/2610.10129/) (2026)

## Abstract (arXiv)

Logic synthesis is a challenging and widely-researched combinatorial optimization problem during integrated circuit (IC) design. It transforms a high-level description of hardware in a programming language like Verilog into an optimized digital circuit netlist, a network of interconnected Boolean logic gates, that implements the function. Spurred by the success of ML in solving combinatorial and graph problems in other domains, there is growing interest in the design of ML-guided logic synthesis tools. Yet, there are no standard datasets or prototypical learning tasks defined for this problem domain. Here, we describe OpenABC-D,a large-scale, labeled dataset produced by synthesizing open source designs with a leading open-source logic synthesis tool and illustrate its use in developing, evaluating and benchmarking ML-guided logic synthesis. OpenABC-D has intermediate and final outputs in the form of 870,000 And-Inverter-Graphs (AIGs) produced from 1500 synthesis runs plus labels such as the optimized node counts, and de-lay. We define a generic learning problem on this dataset and benchmark existing solutions for it. The codes related to dataset creation and benchmark models are available athttps://github.com/NYU-MLDA/OpenABC.git. The dataset generated is available athttps://archive.nyu.edu/handle/2451/63311