# Design Technology Co-Optimization for Neuromorphic Computing

arXiv: https://arxiv.org/abs/2110.08131 · HTML: https://mlsanity.com/paper/2110.08131/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 15 Oct 2021.

## Built on by (most cited first, 1 of 1)

- [Learning in Feedback-driven Recurrent Spiking Neural Networks using full-FORCE Training](https://mlsanity.com/paper/2205.13585/) (2022)

## Abstract (arXiv)

We present a design-technology tradeoff analysis in implementing machine-learning inference on the processing cores of a Non-Volatile Memory (NVM)-based many-core neuromorphic hardware. Through detailed circuit-level simulations for scaled process technology nodes, we show the negative impact of design scaling on read endurance of NVMs, which directly impacts their inference lifetime. At a finer granularity, the inference lifetime of a core depends on 1) the resistance state of synaptic weights programmed on the core (design) and 2) the voltage variation inside the core that is introduced by the parasitic components on current paths (technology). We show that such design and technology characteristics can be incorporated in a design flow to significantly improve the inference lifetime.