# DPUV3INT8: A Compiler View to programmable FPGA Inference Engines

arXiv: https://arxiv.org/abs/2110.04327 · HTML: https://mlsanity.com/paper/2110.04327/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 1 of its 20 references that are in the map.
- First posted on arXiv 8 Oct 2021.

## Builds on (most cited first, 1 of 1)

- [CLBlast: A Tuned OpenCL BLAS Library](https://mlsanity.com/paper/1705.05249/) (2017)

## Abstract (arXiv)

We have a FPGA design, we make it fast, efficient, and tested for a few important examples. Now we must infer a general solution to deploy in the data center. Here, we describe the FPGA DPUV3INT8 design and our compiler effort. The hand-tuned SW-HW solution for Resnet50v1 has (close to) 2 times better images per second (throughput) than our best FPGA implementation; the compiler generalizes the hand written techniques achieving about 1.5 times better performance for the same example, the compiler generalizes the optimizations to a model zoo of networks, and it achieves 80+% HW efficiency.