# DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks

arXiv: https://arxiv.org/abs/2110.00211 · HTML: https://mlsanity.com/paper/2110.00211/

## Key facts

- Cited by 18 papers in the map (data through 14 Oct 2026).
- Builds on 3 of its 18 references that are in the map.
- First posted on arXiv 1 Oct 2021.

## Builds on (most cited first, 3 of 3)

- [Continuous control with deep reinforcement learning](https://mlsanity.com/paper/1509.02971/) (2015)
- [GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2005.00406/) (2020)
- [AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs](https://mlsanity.com/paper/2001.01808/) (2020)

## Built on by (most cited first, 18 of 18)

- [LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits](https://mlsanity.com/paper/2411.12930/) (2024)
- [AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs](https://mlsanity.com/paper/2508.02518/) (2025)
- [INSIGHT: Universal Neural Simulator for Analog Circuits Harnessing Autoregressive Transformers](https://mlsanity.com/paper/2407.07346/) (2024)
- [TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits](https://mlsanity.com/paper/2509.14169/) (2025)
- [HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization](https://mlsanity.com/paper/2511.19669/) (2025)
- [GraCo -- A Graph Composer for Integrated Circuits](https://mlsanity.com/paper/2411.13890/) (2024)
- [DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining](https://mlsanity.com/paper/2502.08949/) (2025)
- [Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks](https://mlsanity.com/paper/2311.17073/) (2023)
- [AI-Guided Codesign Framework for Novel Material and Device Design applied to MTJ-based True Random Number Generators](https://mlsanity.com/paper/2411.01008/) (2024)
- [Emerging ML-AI Techniques for Analog and RF EDA](https://mlsanity.com/paper/2506.00007/) (2025)
- [SPICEMixer - Netlist-Level Circuit Evolution](https://mlsanity.com/paper/2506.01497/) (2025)
- [Report for NSF Workshop on AI for Electronic Design Automation](https://mlsanity.com/paper/2601.14541/) (2026)
- [PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converters](https://mlsanity.com/paper/2601.21984/) (2026)
- [AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuits](https://mlsanity.com/paper/2605.01404/) (2026)
- [Spicing up Genetic Netlist Generation with LLMs](https://mlsanity.com/paper/2608.23317/) (2026)
- [AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing](https://mlsanity.com/paper/2609.25873/) (2026)
- [Inspector: Conversational and Lightweight Analyzer of Analog Circuit Layouts Using LLM and CNNs](https://mlsanity.com/paper/2609.34976/) (2026)
- [THEIA: A Multimodal Dataset and Benchmark for Vision-Language Analysis of Layout](https://mlsanity.com/paper/2609.35035/) (2026)

## Abstract (arXiv)

Analog circuit sizing takes a significant amount of manual effort in a typical design cycle. With rapidly developing technology and tight schedules, bringing automated solutions for sizing has attracted great attention. This paper presents DNN-Opt, a Reinforcement Learning (RL) inspired Deep Neural Network (DNN) based black-box optimization framework for analog circuit sizing. The key contributions of this paper are a novel sample-efficient two-stage deep learning optimization framework leveraging RL actor-critic algorithms, and a recipe to extend it on large industrial circuits using critical device identification. Our method shows 5--30x sample efficiency compared to other black-box optimization methods both on small building blocks and on large industrial circuits with better performance metrics. To the best of our knowledge, this is the first application of DNN-based circuit sizing on industrial scale circuits.