# In-filter Computing For Designing Ultra-light Acoustic Pattern Recognizers

arXiv: https://arxiv.org/abs/2109.06171 · HTML: https://mlsanity.com/paper/2109.06171/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 4 of its 48 references that are in the map.
- First posted on arXiv 11 Sep 2021.

## Builds on (most cited first, 4 of 4)

- [CNN Architectures for Large-Scale Audio Classification](https://mlsanity.com/paper/1609.09430/) (2016)
- [Deep Convolutional Neural Networks and Data Augmentation for Environmental Sound Classification](https://mlsanity.com/paper/1608.04363/) (2016)
- [FPGA Implementation of the CAR Model of the Cochlea](https://mlsanity.com/paper/1503.00504/) (2015)
- [Neuromorphic In-Memory Computing Framework using Memtransistor Cross-bar based Support Vector Machines](https://mlsanity.com/paper/1903.12330/) (2019)

## Built on by (most cited first, 1 of 1)

- [Multiplierless In-filter Computing for tinyML Platforms](https://mlsanity.com/paper/2304.11816/) (2023)

## Abstract (arXiv)

We present a novel in-filter computing framework that can be used for designing ultra-light acoustic classifiers for use in smart internet-of-things (IoTs). Unlike a conventional acoustic pattern recognizer, where the feature extraction and classification are designed independently, the proposed architecture integrates the convolution and nonlinear filtering operations directly into the kernels of a Support Vector Machine (SVM). The result of this integration is a template-based SVM whose memory and computational footprint (training and inference) is light enough to be implemented on an FPGA-based IoT platform. While the proposed in-filter computing framework is general enough, in this paper, we demonstrate this concept using a Cascade of Asymmetric Resonator with Inner Hair Cells (CAR-IHC) based acoustic feature extraction algorithm. The complete system has been optimized using time-multiplexing and parallel-pipeline techniques for a Xilinx Spartan 7 series Field Programmable Gate Array (FPGA). We show that the system can achieve robust classification performance on benchmark sound recognition tasks using only ~ 1.5k Look-Up Tables (LUTs) and ~ 2.8k Flip-Flops (FFs), a significant improvement over other approaches.