# Higher-Order Concurrency for Microcontrollers

arXiv: https://arxiv.org/abs/2108.07805 · HTML: https://mlsanity.com/paper/2108.07805/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 1 of its 29 references that are in the map.
- First posted on arXiv 17 Aug 2021.

## Builds on (most cited first, 1 of 1)

- [Hailstorm : A Statically-Typed, Purely Functional Language for IoT Applications](https://mlsanity.com/paper/2105.13468/) (2021)

## Abstract (arXiv)

Programming microcontrollers involves low-level interfacing with hardware and peripherals that are concurrent and reactive. Such programs are typically written in a mixture of C and assembly using concurrent language extensions (like textttFreeRTOS tasks and textttsemaphores), resulting in unsafe, callback-driven, error-prone and difficult-to-maintain code. We address this challenge by introducing textttSenseVM - a bytecode-interpreted virtual machine that provides a message-passing based textithigher-order concurrency model, originally introduced by Reppy, for microcontroller programming. This model treats synchronous operations as first-class values (called textttEvents) akin to the treatment of first-class functions in functional languages. This primarily allows the programmer to compose and tailor their own concurrency abstractions and, additionally, abstracts away unsafe memory operations, common in shared-memory concurrency models, thereby making microcontroller programs safer, composable and easier-to-maintain. Our VM is made portable via a low-level textitbridge interface, built atop the embedded OS - Zephyr. The bridge is implemented by all drivers and designed such that programming in response to a software message or a hardware interrupt remains uniform and indistinguishable. In this paper we demonstrate the features of our VM through an example, written in a Caml-like functional language, running on the textttnRF52840 and textttSTM32F4 microcontrollers.