# NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

arXiv: https://arxiv.org/abs/2107.07044 · HTML: https://mlsanity.com/paper/2107.07044/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- Builds on 8 of its 20 references that are in the map.
- First posted on arXiv 9 Jul 2021.

## Builds on (most cited first, 8 of 8)

- [Proximal Policy Optimization Algorithms](https://mlsanity.com/paper/1707.06347/) (2017)
- [Neural Message Passing for Quantum Chemistry](https://mlsanity.com/paper/1704.01212/) (2017)
- [Playing Atari with Deep Reinforcement Learning](https://mlsanity.com/paper/1312.5602/) (2013)
- [OpenAI Gym](https://mlsanity.com/paper/1606.01540/) (2016)
- [Chip Placement with Deep Reinforcement Learning](https://mlsanity.com/paper/2004.10746/) (2020)
- [A Deep Reinforcement Learning Approach for Global Routing](https://mlsanity.com/paper/1906.08809/) (2019)
- [Attention Routing: track-assignment detailed routing using attention-based reinforcement learning](https://mlsanity.com/paper/2004.09473/) (2020)
- [Circuit Routing Using Monte Carlo Tree Search and Deep Neural Networks](https://mlsanity.com/paper/2006.13607/) (2020)

## Built on by (most cited first, 7 of 7)

- [DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent](https://mlsanity.com/paper/2412.05311/) (2024)
- [Large Language Model (LLM) for Standard Cell Layout Design Optimization](https://mlsanity.com/paper/2406.06549/) (2024)
- [AIRCHITECT: Learning Custom Architecture Design and Mapping Space](https://mlsanity.com/paper/2108.08295/) (2021)
- [MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning](https://mlsanity.com/paper/2407.18110/) (2024)
- [An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design](https://mlsanity.com/paper/2210.15765/) (2022)
- [Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI](https://mlsanity.com/paper/2506.15907/) (2025)
- [TOPCELL: Topology Optimization of Standard Cell via LLMs](https://mlsanity.com/paper/2604.14237/) (2026)

## Abstract (arXiv)

High quality standard cell layout automation in advanced technology nodes is still challenging in the industry today because of complex design rules. In this paper we introduce an automatic standard cell layout generator called NVCell that can generate layouts with equal or smaller area for over 90% of single row cells in an industry standard cell library on an advanced technology node. NVCell leverages reinforcement learning (RL) to fix design rule violations during routing and to generate efficient placements.