# Multiplierless MP-Kernel Machine For Energy-efficient Edge Devices

arXiv: https://arxiv.org/abs/2106.01958 · HTML: https://mlsanity.com/paper/2106.01958/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- Builds on 12 of its 56 references that are in the map.
- First posted on arXiv 3 Jun 2021.

## Builds on (most cited first, 12 of 12)

- [Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding](https://mlsanity.com/paper/1510.00149/) (2015)
- [XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks](https://mlsanity.com/paper/1603.05279/) (2016)
- [BinaryConnect: Training Deep Neural Networks with binary weights during propagations](https://mlsanity.com/paper/1511.00363/) (2015)
- [Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations](https://mlsanity.com/paper/1609.07061/) (2016)
- [HAWQ: Hessian AWare Quantization of Neural Networks with Mixed-Precision](https://mlsanity.com/paper/1905.03696/) (2019)
- [Towards an Intelligent Edge: Wireless Communication Meets Machine Learning](https://mlsanity.com/paper/1809.00343/) (2018)
- [AdderNet: Do We Really Need Multiplications in Deep Learning?](https://mlsanity.com/paper/1912.13200/) (2019)
- [A Survey on Methods and Theories of Quantized Neural Networks](https://mlsanity.com/paper/1808.04752/) (2018)
- [DeepShift: Towards Multiplication-Less Neural Networks](https://mlsanity.com/paper/1905.13298/) (2019)
- [ShiftAddNet: A Hardware-Inspired Deep Network](https://mlsanity.com/paper/2010.12785/) (2020)
- [A Highly Parallel FPGA Implementation of Sparse Neural Network Training](https://mlsanity.com/paper/1806.01087/) (2018)
- [A Review of Recent Advances of Binary Neural Networks for Edge Computing](https://mlsanity.com/paper/2011.14824/) (2020)

## Built on by (most cited first, 4 of 4)

- [Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning](https://mlsanity.com/paper/2202.05022/) (2022)
- [Process, Bias and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning](https://mlsanity.com/paper/2205.05664/) (2022)
- [A Framework for Analyzing Cross-correlators using Price's Theorem and Piecewise-Linear Decomposition](https://mlsanity.com/paper/2304.09242/) (2023)
- [Multiplierless In-filter Computing for tinyML Platforms](https://mlsanity.com/paper/2304.11816/) (2023)

## Abstract (arXiv)

We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms like intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a Field Programmable Gate Array (FPGA) platform. Our FPGA implementation eliminates the need for DSP units and reduces the number of LUTs. By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from the MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with ~9k LUTs and FFs each for a 256 x 32 sized kernel making it superior in terms of power, performance, and area compared to other comparable implementations.