# An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices

arXiv: https://arxiv.org/abs/2105.13904 · HTML: https://mlsanity.com/paper/2105.13904/

## Key facts

- Cited by 9 papers in the map (data through 14 Oct 2026).
- Builds on 3 of its 27 references that are in the map.
- First posted on arXiv 24 May 2021.

## Builds on (most cited first, 3 of 3)

- [XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks](https://mlsanity.com/paper/1603.05279/) (2016)
- [Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1](https://mlsanity.com/paper/1602.02830/) (2016)
- [High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS](https://mlsanity.com/paper/1909.07514/) (2019)

## Built on by (most cited first, 9 of 9)

- [Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures](https://mlsanity.com/paper/2201.12480/) (2022)
- [MRAM-based Analog Sigmoid Function for In-memory Computing](https://mlsanity.com/paper/2204.09918/) (2022)
- [Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units](https://mlsanity.com/paper/2304.09258/) (2023)
- [A Novel Stochastic LSTM Model Inspired by Quantum Machine Learning](https://mlsanity.com/paper/2305.10212/) (2023)
- [IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architectures](https://mlsanity.com/paper/2304.09252/) (2023)
- [Multi-Objective Neural Architecture Search for In-Memory Computing](https://mlsanity.com/paper/2406.06746/) (2024)
- [PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMs](https://mlsanity.com/paper/2504.01994/) (2025)
- [Reliability-Aware Deployment of DNNs on In-Memory Analog Computing Architectures](https://mlsanity.com/paper/2211.00590/) (2022)
- [CrossNAS: A Cross-Layer Neural Architecture Search Framework for PIM Systems](https://mlsanity.com/paper/2505.22868/) (2025)

## Abstract (arXiv)

In this paper, we develop an in-memory analog computing (IMAC) architecture realizing both synaptic behavior and activation functions within non-volatile memory arrays. Spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices are leveraged to realize sigmoidal neurons as well as binarized synapses. First, it is shown the proposed IMAC architecture can be utilized to realize a multilayer perceptron (MLP) classifier achieving orders of magnitude performance improvement compared to previous mixed-signal and digital implementations. Next, a heterogeneous mixed-signal and mixed-precision CPU-IMAC architecture is proposed for convolutional neural networks (CNNs) inference on mobile processors, in which IMAC is designed as a co-processor to realize fully-connected (FC) layers whereas convolution layers are executed in CPU. Architecture-level analytical models are developed to evaluate the performance and energy consumption of the CPU-IMAC architecture. Simulation results exhibit 6.5% and 10% energy savings for CPU-IMAC based realizations of LeNet and VGG CNN models, for MNIST and CIFAR-10 pattern recognition tasks, respectively.