# FPGA Implementations of Layered MinSum LDPC Decoders Using RCQ Message Passing

arXiv: https://arxiv.org/abs/2104.09480 · HTML: https://mlsanity.com/paper/2104.09480/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 2 of its 16 references that are in the map.
- First posted on arXiv 19 Apr 2021.

## Builds on (most cited first, 2 of 2)

- [Information Bottleneck Decoding of Rate-Compatible 5G-LDPC Codes](https://mlsanity.com/paper/1906.08985/) (2019)
- [A Reconstruction-Computation-Quantization (RCQ) Approach to Node Operations in LDPC Decoding](https://mlsanity.com/paper/2005.07259/) (2020)

## Built on by (most cited first, 1 of 1)

- [Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding](https://mlsanity.com/paper/2111.08920/) (2021)

## Abstract (arXiv)

Non-uniform message quantization techniques such as reconstruction-computation-quantization (RCQ) improve error-correction performance and decrease hardware complexity of low-density parity-check (LDPC) decoders that use a flooding schedule. Layered MinSum RCQ (L-msRCQ) enables message quantization to be utilized for layered decoders and irregular LDPC codes. We investigate field-programmable gate array (FPGA) implementations of L-msRCQ decoders. Three design methods for message quantization are presented, which we name the Lookup, Broadcast, and Dribble methods. The decoding performance and hardware complexity of these schemes are compared to a layered offset MinSum (OMS) decoder. Simulation results on a (16384, 8192) protograph-based raptor-like (PBRL) LDPC code show that a 4-bit L-msRCQ decoder using the Broadcast method can achieve a 0.03 dB improvement in error-correction performance while using 12% fewer registers than the OMS decoder. A Broadcast-based 3-bit L-msRCQ decoder uses 15% fewer lookup tables, 18% fewer registers, and 13% fewer routed nets than the OMS decoder, but results in a 0.09 dB loss in performance.