# A matrix math facility for Power ISA(TM) processors

arXiv: https://arxiv.org/abs/2104.03142 · HTML: https://mlsanity.com/paper/2104.03142/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- Builds on 3 of its 25 references that are in the map.
- First posted on arXiv 7 Apr 2021.

## Builds on (most cited first, 3 of 3)

- [In-Datacenter Performance Analysis of a Tensor Processing Unit](https://mlsanity.com/paper/1704.04760/) (2017)
- [The ARM Scalable Vector Extension](https://mlsanity.com/paper/1803.06185/) (2018)
- [A Transprecision Floating-Point Platform for Ultra-Low Power Computing](https://mlsanity.com/paper/1711.10374/) (2017)

## Built on by (most cited first, 3 of 3)

- [Advancing Direct Convolution using Convolution Slicing Optimization and ISA Extensions](https://mlsanity.com/paper/2303.04739/) (2023)
- [Using MLIR Transform to Design Sliced Convolution Algorithm](https://mlsanity.com/paper/2511.18222/) (2025)
- [CUTEv2: Unified and Configurable Matrix Extension for Diverse CPU Architectures with Minimal Design Overhead](https://mlsanity.com/paper/2604.11615/) (2026)

## Abstract (arXiv)

Power ISA(TM) Version 3.1 has introduced a new family of matrix math instructions, collectively known as the Matrix-Multiply Assist (MMA) facility. The instructions in this facility implement numerical linear algebra operations on small matrices and are meant to accelerate computation-intensive kernels, such as matrix multiplication, convolution and discrete Fourier transform. These instructions have led to a power- and area-efficient implementation of a high throughput math engine in the future POWER10 processor. Performance per core is 4 times better, at constant frequency, than the previous generation POWER9 processor. We also advocate the use of compiler built-ins as the preferred way of leveraging these instructions, which we illustrate through case studies covering matrix multiplication and convolution.