# A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrays

arXiv: https://arxiv.org/abs/2104.02184 · HTML: https://mlsanity.com/paper/2104.02184/

## Key facts

- Cited by 39 papers in the map (data through 14 Oct 2026).
- Builds on 5 of its 14 references that are in the map.
- First posted on arXiv 5 Apr 2021.

## Builds on (most cited first, 5 of 5)

- [PyTorch: An Imperative Style, High-Performance Deep Learning Library](https://mlsanity.com/paper/1912.01703/) (2019)
- [DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training](https://mlsanity.com/paper/2003.06471/) (2020)
- [Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices](https://mlsanity.com/paper/1603.07341/) (2016)
- [RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars](https://mlsanity.com/paper/1809.00072/) (2018)
- [Algorithm for Training Neural Networks on Resistive Device Arrays](https://mlsanity.com/paper/1909.07908/) (2019)

## Built on by (most cited first, 30 of 39)

- [Deep physical neural networks enabled by a backpropagation algorithm for arbitrary physical systems](https://mlsanity.com/paper/2104.13386/) (2021)
- [Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators](https://mlsanity.com/paper/2302.08469/) (2023)
- [Fast offset corrected in-memory training](https://mlsanity.com/paper/2303.04721/) (2023)
- [Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference](https://mlsanity.com/paper/2307.09357/) (2023)
- [AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing](https://mlsanity.com/paper/2305.10459/) (2023)
- [Towards Exact Gradient-based Training on Analog In-memory Computing](https://mlsanity.com/paper/2406.12774/) (2024)
- [Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing](https://mlsanity.com/paper/2305.18416/) (2023)
- [Analog In-memory Training on General Non-ideal Resistive Elements: The Impact of Response Functions](https://mlsanity.com/paper/2502.06309/) (2025)
- [In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning](https://mlsanity.com/paper/2510.02516/) (2025)
- [Gradient-based Neuromorphic Learning on Dynamical RRAM Arrays](https://mlsanity.com/paper/2206.12992/) (2022)
- [AnalogVNN: A fully modular framework for modeling and optimizing photonic neural networks](https://mlsanity.com/paper/2210.10048/) (2022)
- [Efficient transformer adaptation for analog in-memory computing via low-rank adapters](https://mlsanity.com/paper/2411.17367/) (2024)
- [NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities](https://mlsanity.com/paper/2505.02314/) (2025)
- [Dynamic Symmetric Point Tracking: Tackling Non-ideal Reference in Analog In-memory Training](https://mlsanity.com/paper/2602.21321/) (2026)
- [Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architectures](https://mlsanity.com/paper/2201.06703/) (2022)
- [A Cryogenic Memristive Neural Decoder for Fault-tolerant Quantum Error Correction](https://mlsanity.com/paper/2307.09463/) (2023)
- [When In-memory Computing Meets Spiking Neural Networks -- A Perspective on Device-Circuit-System-and-Algorithm Co-design](https://mlsanity.com/paper/2408.12767/) (2024)
- [Regularization-based Framework for Quantization-, Fault- and Variability-Aware Training](https://mlsanity.com/paper/2503.01297/) (2025)
- [Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer](https://mlsanity.com/paper/2505.14303/) (2025)
- [Running Conventional Automatic Speech Recognition on Memristor Hardware: A Simulated Approach](https://mlsanity.com/paper/2505.24721/) (2025)
- [Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing](https://mlsanity.com/paper/2506.00004/) (2025)
- [Memristor-Based Neural Network Accelerators for Space Applications: Enhancing Performance with Temporal Averaging and SIRENs](https://mlsanity.com/paper/2509.04506/) (2025)
- [Circuit realization and hardware linearization of monotone operator equilibrium networks](https://mlsanity.com/paper/2509.13793/) (2025)
- [Energy-convergence trade off for the training of neural networks on bio-inspired hardware](https://mlsanity.com/paper/2509.18121/) (2025)
- [XBTorch: A Unified Framework for Modeling and Co-Design of Crossbar-Based Deep Learning Accelerators](https://mlsanity.com/paper/2601.07086/) (2026)
- [Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converters](https://mlsanity.com/paper/2609.36584/) (2026)
- [SAMSON: Sharpness-Aware Minimization Scaled by Outlier Normalization for Improving DNN Generalization and Robustness](https://mlsanity.com/paper/2211.11561/) (2022)
- [Analog In-Memory Computing with Uncertainty Quantification for Efficient Edge-based Medical Imaging Segmentation](https://mlsanity.com/paper/2403.08796/) (2024)
- [Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays- Part 2: Design Knobs and DNN Accuracy Trends](https://mlsanity.com/paper/2408.05857/) (2024)
- [A Realistic Simulation Framework for Analog/Digital Neuromorphic Architectures](https://mlsanity.com/paper/2409.14918/) (2024)

## Abstract (arXiv)

We introduce the IBM Analog Hardware Acceleration Kit, a new and first of a kind open source toolkit to simulate analog crossbar arrays in a convenient fashion from within PyTorch (freely available at https://github.com/IBM/aihwkit). The toolkit is under active development and is centered around the concept of an "analog tile" which captures the computations performed on a crossbar array. Analog tiles are building blocks that can be used to extend existing network modules with analog components and compose arbitrary artificial neural networks (ANNs) using the flexibility of the PyTorch framework. Analog tiles can be conveniently configured to emulate a plethora of different analog hardware characteristics and their non-idealities, such as device-to-device and cycle-to-cycle variations, resistive device response curves, and weight and output noise. Additionally, the toolkit makes it possible to design custom unit cell configurations and to use advanced analog optimization algorithms such as Tiki-Taka. Moreover, the backward and update behavior can be set to "ideal" to enable hardware-aware training features for chips that target inference acceleration only. To evaluate the inference accuracy of such chips over time, we provide statistical programming noise and drift models calibrated on phase-change memory hardware. Our new toolkit is fully GPU accelerated and can be used to conveniently estimate the impact of material properties and non-idealities of future analog technology on the accuracy for arbitrary ANNs.