# An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform

arXiv: https://arxiv.org/abs/2104.00192 · HTML: https://mlsanity.com/paper/2104.00192/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 7 of its 12 references that are in the map.
- First posted on arXiv 1 Apr 2021.

## Builds on (most cited first, 7 of 7)

- [ORB-SLAM2: an Open-Source SLAM System for Monocular, Stereo and RGB-D Cameras](https://mlsanity.com/paper/1610.06475/) (2016)
- [On-Manifold Preintegration for Real-Time Visual-Inertial Odometry](https://mlsanity.com/paper/1512.02363/) (2015)
- [Navion: A 2mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones](https://mlsanity.com/paper/1809.05780/) (2018)
- [eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform](https://mlsanity.com/paper/1906.05096/) (2019)
- [A Survey of FPGA-Based Robotic Computing](https://mlsanity.com/paper/2009.06034/) (2020)
- [FPGA-based ORB Feature Extraction for Real-Time Visual SLAM](https://mlsanity.com/paper/1710.07312/) (2017)
- [Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines](https://mlsanity.com/paper/2012.01353/) (2020)

## Built on by (most cited first, 1 of 1)

- [iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform](https://mlsanity.com/paper/2104.05112/) (2021)

## Abstract (arXiv)

In our past few years' of commercial deployment experiences, we identify localization as a critical task in autonomous machine applications, and a great acceleration target. In this paper, based on the observation that the visual frontend is a major performance and energy consumption bottleneck, we present our design and implementation of an energy-efficient hardware architecture for ORB (Oriented-Fast and Rotated- BRIEF) based localization system on FPGAs. To support our multi-sensor autonomous machine localization system, we present hardware synchronization, frame-multiplexing, and parallelization techniques, which are integrated in our design. Compared to Nvidia TX1 and Intel i7, our FPGA-based implementation achieves 5.6x and 3.4x speedup, as well as 3.0x and 34.6x power reduction, respectively.