# MF-Net: Compute-In-Memory SRAM for Multibit Precision Inference using Memory-immersed Data Conversion and Multiplication-free Operators

arXiv: https://arxiv.org/abs/2102.00035 · HTML: https://mlsanity.com/paper/2102.00035/

## Key facts

- Cited by 12 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 29 Jan 2021.

## Built on by (most cited first, 12 of 12)

- [Block Walsh-Hadamard Transform Based Binary Layers in Deep Neural Networks](https://mlsanity.com/paper/2201.02711/) (2022)
- [MC-CIM: Compute-in-Memory with Monte-Carlo Dropouts for Bayesian Edge Intelligence](https://mlsanity.com/paper/2111.07125/) (2021)
- [Intelligent Sensing-to-Action for Robust Autonomy at the Edge: Opportunities and Challenges](https://mlsanity.com/paper/2502.02692/) (2025)
- [ADC/DAC-Free Analog Acceleration of Deep Neural Networks with Frequency Transformation](https://mlsanity.com/paper/2309.01771/) (2023)
- [Memory-Immersed Collaborative Digitization for Area-Efficient Compute-in-Memory Deep Learning](https://mlsanity.com/paper/2307.03863/) (2023)
- [Neural Precision Polarization: Simplifying Neural Network Inference with Dual-Level Precision](https://mlsanity.com/paper/2411.05845/) (2024)
- [Multiplication-Avoiding Variant of Power Iteration with Applications](https://mlsanity.com/paper/2110.12065/) (2021)
- [HTMA-Net: Towards Multiplication-Avoiding Neural Networks via Hadamard Transform and In-Memory Computing](https://mlsanity.com/paper/2509.23103/) (2025)
- [ENOS: Energy-Aware Network Operator Search for Hybrid Digital and Compute-in-Memory DNN Accelerators](https://mlsanity.com/paper/2104.05217/) (2021)
- [Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning](https://mlsanity.com/paper/2307.07631/) (2023)
- [Containing Analog Data Deluge at Edge through Frequency-Domain Compression in Collaborative Compute-in-Memory Networks](https://mlsanity.com/paper/2309.11048/) (2023)
- [Learned Queries and Keys Are All You Need: Replacing the Value Projection with Structured Transforms](https://mlsanity.com/paper/2609.36698/) (2026)

## Abstract (arXiv)

We propose a co-design approach for compute-in-memory inference for deep neural networks (DNN). We use multiplication-free function approximators based on ell1 norm along with a co-adapted processing array and compute flow. Using the approach, we overcame many deficiencies in the current art of in-SRAM DNN processing such as the need for digital-to-analog converters (DACs) at each operating SRAM row/column, the need for high precision analog-to-digital converters (ADCs), limited support for multi-bit precision weights, and limited vector-scale parallelism. Our co-adapted implementation seamlessly extends to multi-bit precision weights, it doesn't require DACs, and it easily extends to higher vector-scale parallelism. We also propose an SRAM-immersed successive approximation ADC (SA-ADC), where we exploit the parasitic capacitance of bit lines of SRAM array as a capacitive DAC. Since the dominant area overhead in SA-ADC comes due to its capacitive DAC, by exploiting the intrinsic parasitic of SRAM array, our approach allows low area implementation of within-SRAM SA-ADC. Our 8×62 SRAM macro, which requires a 5-bit ADC, achieves ~105 tera operations per second per Watt (TOPS/W) with 8-bit input/weight processing at 45 nm CMOS.