# Accelerating ODE-Based Neural Networks on Low-Cost FPGAs

arXiv: https://arxiv.org/abs/2012.15465 · HTML: https://mlsanity.com/paper/2012.15465/

## Key facts

- Cited by 3 papers in the map (data through 13 Oct 2026).
- First posted on arXiv 31 Dec 2020.

## Built on by (most cited first, 3 of 3)

- [A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs](https://mlsanity.com/paper/2107.12824/) (2021)
- [Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures](https://mlsanity.com/paper/2512.06113/) (2025)
- [Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics](https://mlsanity.com/paper/2512.23767/) (2025)

## Abstract (arXiv)

ODENet is a deep neural network architecture in which a stacking structure of ResNet is implemented with an ordinary differential equation (ODE) solver. It can reduce the number of parameters and strike a balance between accuracy and performance by selecting a proper solver. It is also possible to improve the accuracy while keeping the same number of parameters on resource-limited edge devices. In this paper, using Euler method as an ODE solver, a part of ODENet is implemented as a dedicated logic on a low-cost FPGA (Field-Programmable Gate Array) board, such as PYNQ-Z2 board. As ODENet variants, reduced ODENets (rODENets) each of which heavily uses a part of ODENet layers and reduces/eliminates some layers differently are proposed and analyzed for low-cost FPGA implementation. They are evaluated in terms of parameter size, accuracy, execution time, and resource utilization on the FPGA. The results show that an overall execution time of an rODENet variant is improved by up to 2.66 times compared to a pure software execution while keeping a comparable accuracy to the original ODENet.