# DeepNVM++: Cross-Layer Modeling and Optimization Framework of Non-Volatile Memories for Deep Learning

arXiv: https://arxiv.org/abs/2012.04559 · HTML: https://mlsanity.com/paper/2012.04559/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 8 Dec 2020.

## Built on by (most cited first, 4 of 4)

- [QAPPA: Quantization-Aware Power, Performance, and Area Modeling of DNN Accelerators](https://mlsanity.com/paper/2205.08648/) (2022)
- [QADAM: Quantization-Aware DNN Accelerator Modeling for Pareto-Optimality](https://mlsanity.com/paper/2205.13045/) (2022)
- [QUIDAM: A Framework for Quantization-Aware DNN Accelerator and Model Co-Exploration](https://mlsanity.com/paper/2206.15463/) (2022)
- [Efficient Deep Learning Using Non-Volatile Memory Technology](https://mlsanity.com/paper/2206.13601/) (2022)

## Abstract (arXiv)

Non-volatile memory (NVM) technologies such as spin-transfer torque magnetic random access memory (STT-MRAM) and spin-orbit torque magnetic random access memory (SOT-MRAM) have significant advantages compared to conventional SRAM due to their non-volatility, higher cell density, and scalability features. While previous work has investigated several architectural implications of NVM for generic applications, in this work we present DeepNVM++, a framework to characterize, model, and analyze NVM-based caches in GPU architectures for deep learning (DL) applications by combining technology-specific circuit-level models and the actual memory behavior of various DL workloads. We present both iso-capacity and iso-area performance and energy analysis for systems whose last-level caches rely on conventional SRAM and emerging STT-MRAM and SOT-MRAM technologies. In the iso-capacity case, STT-MRAM and SOT-MRAM provide up to 3.8x and 4.7x energy-delay product (EDP) reduction and 2.4x and 2.8x area reduction compared to conventional SRAM, respectively. Under iso-area assumptions, STT-MRAM and SOT-MRAM provide up to 2x and 2.3x EDP reduction and accommodate 2.3x and 3.3x cache capacity when compared to SRAM, respectively. We also perform a scalability analysis and show that STT-MRAM and SOT-MRAM achieve orders of magnitude EDP reduction when compared to SRAM for large cache capacities. Our comprehensive cross-layer framework is demonstrated on STT-/SOT-MRAM technologies and can be used for the characterization, modeling, and analysis of any NVM technology for last-level caches in GPUs for DL applications.