# Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors

arXiv: https://arxiv.org/abs/2011.04107 · HTML: https://mlsanity.com/paper/2011.04107/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 8 Nov 2020.

## Built on by (most cited first, 1 of 1)

- [Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators](https://mlsanity.com/paper/2501.17567/) (2025)

## Abstract (arXiv)

The main design principles in computer architecture have recently shifted from a monolithic scaling-driven approach to the development of heterogeneous architectures that tightly co-integrate multiple specialized processor and memory chiplets. In such data-hungry multi-chip architectures, current Networks-in-Package (NiPs) may not be enough to cater to their heterogeneous and fast-changing communication demands. This position paper makes the case for wireless in-package nanonetworking as the enabler of efficient and versatile wired-wireless interconnect fabrics for massive heterogeneous processors. To that end, the use of graphene-based antennas and transceivers with unique frequency-beam reconfigurability in the terahertz band is proposed. The feasibility of such a nanonetworking vision and the main research challenges towards its realization are analyzed from the technological, communications, and computer architecture perspectives.