# ASSURE: RTL Locking Against an Untrusted Foundry

arXiv: https://arxiv.org/abs/2010.05344 · HTML: https://mlsanity.com/paper/2010.05344/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 11 Oct 2020.

## Built on by (most cited first, 3 of 3)

- [VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding](https://mlsanity.com/paper/2503.13116/) (2025)
- [Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks](https://mlsanity.com/paper/2107.08695/) (2021)
- [Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities](https://mlsanity.com/paper/2107.01915/) (2021)

## Abstract (arXiv)

Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (IC) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed the semantic information into the netlist. We propose ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description. The RTL approach has three advantages: (i) it allows designers to obfuscate IP cores generated with many different methods (e.g., hardware generators, high-level synthesis tools, and pre-existing IPs). (ii) it obfuscates the semantics of an IC before logic synthesis; (iii) it does not require modifications to EDA flows. We perform a cost and security assessment of ASSURE.