# FPGA Implementation of Simplified Spiking Neural Network

arXiv: https://arxiv.org/abs/2010.01200 · HTML: https://mlsanity.com/paper/2010.01200/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 2 Oct 2020.

## Built on by (most cited first, 4 of 4)

- [Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge](https://mlsanity.com/paper/2401.01141/) (2024)
- [SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA](https://mlsanity.com/paper/2404.03714/) (2024)
- [Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking Neurons](https://mlsanity.com/paper/2506.13268/) (2025)
- [Energy-Aware FPGA Implementation of Spiking Neural Network with LIF Neurons](https://mlsanity.com/paper/2411.01628/) (2024)

## Abstract (arXiv)

Spiking Neural Networks (SNN) are third-generation Artificial Neural Networks (ANN) which are close to the biological neural system. In recent years SNN has become popular in the area of robotics and embedded applications, therefore, it has become imperative to explore its real-time and energy-efficient implementations. SNNs are more powerful than their predecessors because they encode temporal information and use biologically plausible plasticity rules. In this paper, a simpler and computationally efficient SNN model using FPGA architecture is described. The proposed model is validated on a Xilinx Virtex 6 FPGA and analyzes a fully connected network which consists of 800 neurons and 12,544 synapses in real-time.