# A general approach for identifying hierarchical symmetry constraints for analog circuit layout

arXiv: https://arxiv.org/abs/2010.00051 · HTML: https://mlsanity.com/paper/2010.00051/

## Key facts

- Cited by 9 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 30 Sep 2020.

## Built on by (most cited first, 9 of 9)

- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [TAG: Learning Circuit Spatial Embedding From Layouts](https://mlsanity.com/paper/2209.03465/) (2022)
- [Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits](https://mlsanity.com/paper/2312.14405/) (2023)
- [GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification](https://mlsanity.com/paper/2508.19393/) (2025)
- [A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation](https://mlsanity.com/paper/2204.09579/) (2022)
- [Circuit Diagram Retrieval Based on Hierarchical Circuit Graph Representation](https://mlsanity.com/paper/2503.11658/) (2025)
- [Emerging ML-AI Techniques for Analog and RF EDA](https://mlsanity.com/paper/2506.00007/) (2025)
- [The Dark Side: Security Concerns in Machine Learning for EDA](https://mlsanity.com/paper/2203.10597/) (2022)
- [Intelligent Circuit Design and Implementation with Machine Learning](https://mlsanity.com/paper/2206.03032/) (2022)

## Abstract (arXiv)

Analog layout synthesis requires some elements in the circuit netlist to be matched and placed symmetrically. However, the set of symmetries is very circuit-specific and a versatile algorithm, applicable to a broad variety of circuits, has been elusive. This paper presents a general methodology for the automated generation of symmetry constraints, and applies these constraints to guide automated layout synthesis. While prior approaches were restricted to identifying simple symmetries, the proposed method operates hierarchically and uses graph-based algorithms to extract multiple axes of symmetry within a circuit. An important ingredient of the algorithm is its ability to identify arrays of repeated structures. In some circuits, the repeated structures are not perfect replicas and can only be found through approximate graph matching. A fast graph neural network based methodology is developed for this purpose, based on evaluating the graph edit distance. The utility of this algorithm is demonstrated on a variety of circuits, including operational amplifiers, data converters, equalizers, and low-noise amplifiers.