# AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

arXiv: https://arxiv.org/abs/2009.14381 · HTML: https://mlsanity.com/paper/2009.14381/

## Key facts

- Cited by 25 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 30 Sep 2020.

## Built on by (most cited first, 25 of 25)

- [A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware](https://mlsanity.com/paper/2306.14052/) (2023)
- [Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis](https://mlsanity.com/paper/2406.09606/) (2024)
- [LLM-DSE: Searching Accelerator Parameters with LLM Agents](https://mlsanity.com/paper/2505.12188/) (2025)
- [Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis](https://mlsanity.com/paper/2410.19225/) (2024)
- [HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond](https://mlsanity.com/paper/2405.00820/) (2024)
- [LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning](https://mlsanity.com/paper/2504.21187/) (2025)
- [iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs](https://mlsanity.com/paper/2505.22086/) (2025)
- [Evolution of Optimization Algorithms for Global Placement via Large Language Models](https://mlsanity.com/paper/2504.17801/) (2025)
- [Bring Your Own Codegen to Deep Learning Compiler](https://mlsanity.com/paper/2105.03215/) (2021)
- [Efficient Task Transfer for HLS DSE](https://mlsanity.com/paper/2408.13270/) (2024)
- [Learning to Compare Hardware Designs for High-Level Synthesis](https://mlsanity.com/paper/2409.13138/) (2024)
- [CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference](https://mlsanity.com/paper/2511.16395/) (2025)
- [AgRefactor: Self-Evolving Agentic Workflow for HLS Compatibility and Performance](https://mlsanity.com/paper/2606.30949/) (2026)
- [GANDSE: Generative Adversarial Network based Design Space Exploration for Neural Network Accelerator Design](https://mlsanity.com/paper/2208.00800/) (2022)
- [ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis](https://mlsanity.com/paper/2507.03255/) (2025)
- [Iceberg: Enhancing HLS Modeling with Synthetic Data](https://mlsanity.com/paper/2507.09948/) (2025)
- [Report for NSF Workshop on AI for Electronic Design Automation](https://mlsanity.com/paper/2601.14541/) (2026)
- [Agent Factories for High Level Synthesis: How Far Can General-Purpose Coding Agents Go in Hardware Optimization?](https://mlsanity.com/paper/2603.25719/) (2026)
- [Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verification](https://mlsanity.com/paper/2606.28409/) (2026)
- [Pyxis: An Open-Source Performance Dataset of Sparse Accelerators](https://mlsanity.com/paper/2110.04280/) (2021)
- [Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks](https://mlsanity.com/paper/2111.08848/) (2021)
- [ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation](https://mlsanity.com/paper/2305.10838/) (2023)
- [A3D: Agentic AI flow for autonomous Accelerator Design](https://mlsanity.com/paper/2605.15237/) (2026)
- [HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation](https://mlsanity.com/paper/2608.06791/) (2026)
- [SyntheticHLS: Building Diverse Synthetic High-Level Synthesis Datasets using LLMs](https://mlsanity.com/paper/2610.00106/) (2026)

## Abstract (arXiv)

Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS), accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve the optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. To address this problem, we propose an automated DSE framework-AutoDSE- that leverages a bottleneck-guided coordinate optimizer to systematically find a better design point. AutoDSE detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. The experimental results show that AutoDSE is able to identify the design point that achieves, on the geometric mean, 19.9x speedup over one CPU core for Machsuite and Rodinia benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx Vitis libraries, AutoDSE can reduce their optimization pragmas by 26.38x while achieving similar performance. With less than one optimization pragma per design on average, we are making progress towards democratizing customizable computing by enabling software programmers to design efficient FPGA accelerators.