# DMR-based Technique for Fault Tolerant AES S-box Architecture

arXiv: https://arxiv.org/abs/2009.05329 · HTML: https://mlsanity.com/paper/2009.05329/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 11 Sep 2020.

## Built on by (most cited first, 1 of 1)

- [A Novel Fault-Tolerant Logic Style with Self-Checking Capability](https://mlsanity.com/paper/2306.00844/) (2023)

## Abstract (arXiv)

This paper presents a high-throughput fault-resilient hardware implementation of AES S-box, called HFS-box. If a transient natural or even malicious fault in each pipeline stage is detected, the corresponding error signal becomes high and as a result, the control unit holds the output of our proposed DMR voter till the fault effect disappears. The proposed low-cost HFS-box provides a high capability of fault-tolerant against transient faults with any duration by putting low area overhead, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original implementation.