# HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis

arXiv: https://arxiv.org/abs/2009.00871 · HTML: https://mlsanity.com/paper/2009.00871/

## Key facts

- Cited by 9 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 2 Sep 2020.

## Built on by (most cited first, 9 of 9)

- [A Survey of Machine Learning for Computer Architecture and Systems](https://mlsanity.com/paper/2102.07952/) (2021)
- [PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs](https://mlsanity.com/paper/2201.10114/) (2022)
- [HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond](https://mlsanity.com/paper/2405.00820/) (2024)
- [HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis](https://mlsanity.com/paper/2302.10977/) (2023)
- [An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators](https://mlsanity.com/paper/2308.12120/) (2023)
- [A Benchmark on Directed Graph Representation Learning in Hardware Designs](https://mlsanity.com/paper/2410.06460/) (2024)
- [ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis](https://mlsanity.com/paper/2507.03255/) (2025)
- [Deep Inverse Design for High-Level Synthesis](https://mlsanity.com/paper/2407.08797/) (2024)
- [DiffHLS: Differential Learning for High-Level Synthesis QoR Prediction with GNNs and LLM Code Embeddings](https://mlsanity.com/paper/2604.09240/) (2026)

## Abstract (arXiv)

High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HLS-based applications at an early design stage. To overcome this problem, we introduce HL-Pow, a power modeling framework for FPGA HLS based on state-of-the-art machine learning techniques. HL-Pow incorporates an automated feature construction flow to efficiently identify and extract features that exert a major influence on power consumption, simply based upon HLS results, and a modeling flow that can build an accurate and generic power model applicable to a variety of designs with HLS. By using HL-Pow, the power evaluation process for FPGA designs can be significantly expedited because the power inference of HL-Pow is established on HLS instead of the time-consuming register-transfer level (RTL) implementation flow. Experimental results demonstrate that HL-Pow can achieve accurate power modeling that is only 4.67% (24.02 mW) away from onboard power measurement. To further facilitate power-oriented optimizations, we describe a novel design space exploration (DSE) algorithm built on top of HL-Pow to trade off between latency and power consumption. This algorithm can reach a close approximation of the real Pareto frontier while only requiring running HLS flow for 20% of design points in the entire design space.