# ALIGN: A System for Automating Analog Layout

arXiv: https://arxiv.org/abs/2008.10682 · HTML: https://mlsanity.com/paper/2008.10682/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 24 Aug 2020.

## Built on by (most cited first, 8 of 8)

- [Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2411.15212/) (2024)
- [FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design](https://mlsanity.com/paper/2505.21923/) (2025)
- [OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation](https://mlsanity.com/paper/2601.19439/) (2026)
- [ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings](https://mlsanity.com/paper/2511.07658/) (2025)
- [Emerging ML-AI Techniques for Analog and RF EDA](https://mlsanity.com/paper/2506.00007/) (2025)
- [NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation](https://mlsanity.com/paper/2608.12197/) (2026)
- [Advancing Routing-Awareness in Analog ICs Floorplanning](https://mlsanity.com/paper/2510.15387/) (2025)
- [LLMs for Analog Circuit Design Continuum (ACDC)](https://mlsanity.com/paper/2512.09199/) (2025)

## Abstract (arXiv)

ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an output GDSII layout, specific to a given technology, as specified by a set of design rules. The flow first automatically detects hierarchies in the circuit netlist and translates layout synthesis to a problem of hierarchical block assembly. At the lowest level, parameterized cells are generated using an abstraction of the design rules; these blocks are then assembled under geometric and electrical constraints to build the circuit layout. ALIGN has been applied to generate layouts for a diverse set of analog circuit families: low frequency analog blocks, wireline circuits, wireless circuits, and power delivery circuits.