# A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment

arXiv: https://arxiv.org/abs/2007.01820 · HTML: https://mlsanity.com/paper/2007.01820/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 2 Jul 2020.

## Built on by (most cited first, 3 of 3)

- [AI/ML Algorithms and Applications in VLSI Design and Technology](https://mlsanity.com/paper/2202.10015/) (2022)
- [Deep Learning Meets Adaptive Filtering: A Stein's Unbiased Risk Estimator Approach](https://mlsanity.com/paper/2307.16708/) (2023)
- [Adaptive Processor Frequency Adjustment for Mobile Edge Computing with Intermittent Energy Supply](https://mlsanity.com/paper/2102.05449/) (2021)

## Abstract (arXiv)

A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within a baseline processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting a speedup of 70% and energy reduction of 30% with coarse-grained ML classification. A speedup of 89% is demonstrated with finer granularities with 15.5% reduction in energy consumption.