# Efficient Neural Network Deployment for Microcontroller

arXiv: https://arxiv.org/abs/2007.01348 · HTML: https://mlsanity.com/paper/2007.01348/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 2 Jul 2020.

## Built on by (most cited first, 7 of 7)

- [Efficient Neural Networks for Tiny Machine Learning: A Comprehensive Review](https://mlsanity.com/paper/2311.11883/) (2023)
- [PermuQuant: Lowering Per-Group Quantization Error by Reordering Channels for Diffusion Models](https://mlsanity.com/paper/2605.09503/) (2026)
- [Design Automation for Fast, Lightweight, and Effective Deep Learning Models: A Survey](https://mlsanity.com/paper/2208.10498/) (2022)
- [Unsupervised Ensemble Methods for Anomaly Detection in PLC-based Process Control](https://mlsanity.com/paper/2302.02097/) (2023)
- [Time Scale Network: A Shallow Neural Network For Time Series Data](https://mlsanity.com/paper/2311.06170/) (2023)
- [Separate, Dynamic and Differentiable (SMART) Pruner for Block/Output Channel Pruning on Computer Vision Tasks](https://mlsanity.com/paper/2403.19969/) (2024)
- [Deep Compression for PyTorch Model Deployment on Microcontrollers](https://mlsanity.com/paper/2103.15972/) (2021)

## Abstract (arXiv)

Edge computing for neural networks is getting important especially for low power applications and offline devices. TensorFlow Lite and PyTorch Mobile were released for this purpose. But they mainly support mobile devices instead of microcontroller level yet. Microcontroller support is an emerging area now. There are many approaches to reduce network size and compute load like pruning, binarization and layer manipulation i.e. operator reordering. This paper is going to explore and generalize convolution neural network deployment for microcontrollers with two novel optimization proposals offering memory saving and compute efficiency in 2D convolutions as well as fully connected layers. The first one is in-place max-pooling, if the stride is greater than or equal to pooling kernel size. The second optimization is to use ping-pong buffers between layers to reduce memory consumption significantly. The memory savings and performance will be compared with CMSIS-NN framework developed for ARM Cortex-M CPUs. The final purpose is to develop a tool consuming PyTorch model with trained network weights, and it turns into an optimized inference engine(forward pass) in C/C++ for low memory(kilobyte level) and limited computing capable microcontrollers.