# An Efficient Accelerator Design Methodology for Deformable Convolutional Networks

arXiv: https://arxiv.org/abs/2006.05238 · HTML: https://mlsanity.com/paper/2006.05238/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 9 Jun 2020.

## Built on by (most cited first, 3 of 3)

- [Efficient Deformable ConvNets: Rethinking Dynamic and Sparse Operator for Vision Applications](https://mlsanity.com/paper/2401.06197/) (2024)
- [Pupil-Adaptive 3D Holography Beyond Coherent Depth-of-Field](https://mlsanity.com/paper/2409.00028/) (2024)
- [big.LITTLE Vision Transformer for Efficient Visual Recognition](https://mlsanity.com/paper/2410.10267/) (2024)

## Abstract (arXiv)

Deformable convolutional networks have demonstrated outstanding performance in object recognition tasks with an effective feature extraction. Unlike standard convolution, the deformable convolution decides the receptive field size using dynamically generated offsets, which leads to an irregular memory access. Especially, the memory access pattern varies both spatially and temporally, making static optimization ineffective. Thus, a naive implementation would lead to an excessive memory footprint. In this paper, we present a novel approach to accelerate deformable convolution on FPGA. First, we propose a novel training method to reduce the size of the receptive field in the deformable convolutional layer without compromising accuracy. By optimizing the receptive field, we can compress the maximum size of the receptive field by 12.6 times. Second, we propose an efficient systolic architecture to maximize its efficiency. We then implement our design on FPGA to support the optimized dataflow. Experimental results show that our accelerator achieves up to 17.25 times speedup over the state-of-the-art accelerator.