# A Unified Hardware Architecture for Convolutions and Deconvolutions in CNN

arXiv: https://arxiv.org/abs/2006.00053 · HTML: https://mlsanity.com/paper/2006.00053/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 29 May 2020.

## Built on by (most cited first, 2 of 2)

- [Programmable FPGA-based Memory Controller](https://mlsanity.com/paper/2108.09601/) (2021)
- [SwiftChannel: Algorithm-Hardware Co-Design for Deep Learning-Based 5G Channel Estimation](https://mlsanity.com/paper/2605.01931/) (2026)

## Abstract (arXiv)

In this paper, a scalable neural network hardware architecture for image segmentation is proposed. By sharing the same computing resources, both convolution and deconvolution operations are handled by the same process element array. In addition, access to on-chip and off-chip memories is optimized to alleviate the burden introduced by partial sum. As an example, SegNet-Basic has been implemented using the proposed unified architecture by targeting on Xilinx ZC706 FPGA, which achieves the performance of 151.5 GOPS and 94.3 GOPS for convolution and deconvolution respectively. This unified convolution/deconvolution design is applicable to other CNNs with deconvolution.