# Mining Message Flows from System-on-Chip Execution Traces

arXiv: https://arxiv.org/abs/2005.11221 · HTML: https://mlsanity.com/paper/2005.11221/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 22 May 2020.

## Built on by (most cited first, 3 of 3)

- [Deep Bidirectional Transformers for SoC Flow Specification Mining](https://mlsanity.com/paper/2203.13182/) (2022)
- [Mining SoC Message Flows with Attention Model](https://mlsanity.com/paper/2209.07929/) (2022)
- [AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs](https://mlsanity.com/paper/2604.15359/) (2026)

## Abstract (arXiv)

Comprehensive and well-defined specifications are necessary to perform rigorous and thorough validation of system-on-chip (SoC) designs. Message flows specify how components of an SoC design communicate and coordinate with each other to realize various system functions. Message flow specifications are essential for efficient system-level validation and debug for SoC designs. However, in practice such specifications are usually not available, often ambiguous, incomplete, or even contain errors. This paper addresses that problem by proposing a specification mining framework, FlowMiner, that automatically extracts message flows from SoC execution traces, which, unlike software traces, show a high degree of concurrency. A set of inference rules and optimization techniques are presented to improve mining performance and reduce mining complexity. Evaluation of this framework in several experiments shows promising results.